DS531 Datasheet, PDF (35/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Specification Exceptions
There are few differences that should be noted by the reader of this specification who also reads the IBM PLB v4.6
specification.
PLB Bus Structure
The Xilinx® PLB provides the full PLB bus structure. No external OR gates are required for the slave input data.
Each PLB slave connects directly to the Xilinx PLB as shown in Figure 1, page 2.
I/O Signals
The master interface signals and many of the PLB signals have been combined into a bus with an index that varies
with the number of masters. This modification more easily supports the parameterization of the number of masters
and the number of slaves supported by the Xilinx PLB.
Signals that have the master designator of Mn in the signal name in the IBM PLB specification have a master
designator of M in the signal name in this document. For example, the signal called PLB_MnReabitrate in the
IBM specification is called PLB_MRearbitrate here. Similarly, Mn_RNW is called M_RNW.
The optional parity concept of PLB v4.6 is not supported. No parity signals are included in the ports.
Differences between the PLB v4.6 and the v3.4
The Xilinx PLB v4.6 bus logic core, the subject of this data sheet, is derived from the PLB v3.4 core. The major
difference between the Xilinx PLB v4.6 and Xilinx PLB v3.4 cores are:
• Maximum data width of 128 bits versus 64 bits.
• M_UABus and PLB_UABus signals added to allow address to grow beyond 32 bits. Currently, all Xilinx soft IP
and EDK tool only utilize 32-bits of the initial PLB v4.6 implementation. The UABus is included as a required
port connection on peripherals, but is driven to zeros by Masters and internally ignored by Slave IP devices.
The PLB v4.6 upper address bus will be included in the required port interface for peripherals and included in
the bus structure multiplexing by the arbiter.
• PLB_MTimeout signal added. If no slave responds to the PAValid assertion, the arbiter asserts the
PLB_MTimeout signal for one clock. In the PLB v3.4 version the arbiter had responsibility to complete the
address acknowledge and data acknowledges (with error qualification on the data acknowledges).
• SL_MIRQ and PLB_MIRQ signals added. These allow any slave to signal an event deemed important to any
master.
• Sl_MErr and PLB_MErr signals split into separate read and write versions: SL_MWrErr, Sl_MRdErr,
PLB_MWrErr and PLB_MRdErr.
• PLB_pendReq and PLB_pendPri signals split into separate read and write version: PLB_wrPendReq,
PLB_rdPendReq, PLB_wrPendPri and PLB_rdPendPri.
• 16-bit M_TAttribute and PLB_TAttribute signals added. The compressed, guarded and ordered
qualifiers are now expressed as TAttribute values, and separate signals for these qualifiers are no longer
present.
DS531 September 21, 2010
www.xilinx.com
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Product Specification