DS531 Datasheet, PDF (19/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Table 4: Parameter-Port Dependencies (Cont’d)
Generic
or Port
Name
Affects
P93 PLB_SMRdErr[0:C_PLBV46_
NUM_MASTERS-1]
P94 PLB_SMWrErr[0:C_PLBV46_
NUM_MASTERS-1]
P95 PLB_Sssize[0:1]
Depends
Relationship Description
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
PLB Registers
The PLB, when configured as a shared bus (C_P2P = 0), may optionally contain DCR-accessible registers to provide
error address and status information for attempted transactions that did not get a response from any slave. These
registers are not available when configured as a point-to-point bus. In what follows, the term error refers to such a
missing response, which is detected by the time out mechanism of the arbiter. If the design has been parameterized
to contain a DCR interface (C_DCR_INTFCE = 1), the registers shown in Table 5 are present.
Note: The base address for these registers is set in the parameter C_BASEADDR.
Table 5: PLB DCR Registers (Available only in Shared Bus Configuration)
Register Name
Description
DCR Address
PESR_MERR_DETECT
Master Error Detect Bits
C_BASEADDR + 0x00
PESR_MDRIVE_PEAR
Master Driving PEAR
C_BASEADDR + 0x01
PESR_RNW_ERR
Read/Write Error
C_BASEADDR + 0x02
PESR_LCK_ERR
Lock Error Bit
C_BASEADDR + 0x03
PEAR_ADDR
PLB Error Address
C_BASEADDR + 0x04
PEAR_BYTE_EN
PLB Error Byte Enables
C_BASEADDR + 0x05
PEAR_SIZE_TYPE
PLB Size and Type
C_BASEADDR + 0x06
PACR
PLB Control Register
C_BASEADDR + 0x07
Access
Read/Write
Read
Read
Read
Read⁽¹⁾
Read/Write
Notes:
1. These registers can be written if the Test Enable bit is asserted in the PACR.
DS531 September 21, 2010
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Product Specification