DS531 Datasheet, PDF (28/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Bus Arbitration
The PLB v4.6 arbitration type is selected using the C_ARB_TYPE design parameter. When C_ARB_TYPE = 0, the
arbitration type is a fixed priority arbitration as discussed in "Basic Operation."
When C_ARB_TYPE = 1, the arbitration logic is configured in a round robin scheme. The round robin
implementation on the PLB v4.6 is such that the last master to win arbitration and be granted the bus, will be the
lowest priority available master to be granted the bus in the next arbitration cycle. The arbitration cycle is indicated
by either the assertion of a Sl_AddrAck, Sl_reArbitrate, or a PLB time out condition. Round robin arbitration
keeps an embedded priority scheme fixed amongst the masters in the system and rotates the priority ordering
based on the last master to win the bus. The arbiter is only able to arbitrate on requesting masters indicated by the
M_Request signals at the arbitration clock cycle.
The round robin scheme, allows masters that may have been starved for the bus, a fair chance of being granted the
bus. An example of round robin implementation with C_NUM_MASTERS = 3 is shown in Figure 16.
X-Ref Target - Figure 16
M_Request(0)
M_Request(1)
M_Request(2)
Arbitration Cycle
Granted Bus Master
Embedded RR
Master Priority
M0
Ordering for Next
M1
M2
Arbitration Cycle
M0 M1
M1
M2
M2
M0
M0
M1
M2 M0 M2 M0 M1 M2
M0
M1 M0 M1 M2 M0
M1
M2 M1 M2 M0 M1
M2
M0 M2 M0 M1 M2
Figure 16: Example of Round Robin Arbitration
M1 M2
M0 M2 M0
M1 M0 M1
M2 M1 M2
DS531_16_061608
Watchdog Timer
The PLB watchdog timer is used to generate the PLB_MTimeout response when no slave responds. The watchdog
time is set to 16 clock cycles.
Reset Logic
The PLB v4.6 does not include any power-on reset circuitry to ensure that a PLB reset is generated upon power-on
if no external reset (Sys_Rst) is provided. It is the assumption in PLB v4.6 systems, that the designer will include the
proc_sys_reset core to ensure a power-on reset is asserted for at least 16 clock cycles.
The reset logic in the PLB v4.6 core will provide one stage of synchronization from the external reset (Sys_Rst) to
the output reset signals, PLB_Rst, SPLB_Rst, and MPLB_Rst. The PLB reset is synchronous to the PLB clock.
The additional slave and master vectorized reset signals (SPLB_Rst and MPLB_Rst), have identical timing
characteristics as the PLB reset (PLB_Rst).
DS531 September 21, 2010
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Product Specification