DS531 Datasheet, PDF (36/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISE
Embedded Edition software (EDK).
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.
For information on pricing and availability of other Xilinx LogiCORE modules and software, please contact your
local Xilinx sales representative.
Support
Xilinx provides technical support for this LogiCORE IP product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Reference Documents
The following documents contain reference information important to understanding the Xilinx PLB design.
1. DS400 Processor Local Bus (PLB) v3.4
2. IBM 128-Bit Processor Local Bus Architectural Specification (v4.6)
3. IBM 32-Bit Device Control Register Bus Architecture Specifications, Version 2.9
List of Acronyms
Acronym
BFM
CPU
DCR
FPGA
I/O
IP
PLB
VHDL
Spelled Out
Basic Functional Model
Central Processing Unit
Device Control Register
Field Programmable Gate Array
Input/Output
Intellectual Property
Processor Local Bus
VHSIC Hardware Description Language (VHSIC an acronym for Very High-Speed Integrated Circuits)
DS531 September 21, 2010
www.xilinx.com
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Product Specification