DS531 Datasheet, PDF (5/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Figure 4 illustrates an example of a delayed Sl_addrAck assertion to the secondary address valid indicator. In this
case, the PLB_SAValid will be promoted to the PLB_PAValid if the primary transaction completes (with the
assertion of Sl_rdComp) prior to the Sl_addrAck.
X-Ref Target - Figure 4
PLB_Clk
M_Request
M_RNW
PLB_PAValid
PLB_SAValid
PLB_RNW
PLB_rdPrim
PLB_wrPrim
Sl_addrAck
Sl_reArbitrate
Sl_rdComp
Sl_wrComp
1
2
2
1
2
1
2
DS531_04_061608
Figure 4: Point-to-Point Address Pipelining (Secondary to Primary Promotion)
Figure 5 illustrates back to back read requests followed by a subsequent write request of the master. With separate
read and write data buses on the PLB, the arbiter is capable of asserting PAValid for a subsequent write operation
prior to the previous read operations completing.
X-Ref Target - Figure 5
PLB_Clk
M_Request
M_RNW
PLB_PAValid
PLB_SAValid
PLB_RNW
PLB_rdPrim
PLB_wrPrim
Sl_addrAck
Sl_reArbitrate
Sl_rdComp
Sl_wrComp
1
3
2
1
2
3
1
2
3
DS531_05_061608
Figure 5: Pipelined Read Transactions with Subsequent Write
DS531 September 21, 2010
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