DS531 Datasheet, PDF (23/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Table 8: PLB PESR_LCK_ERR Bit Definitions
Bit(s)
Name
Core Reset
Access Value
0 to
Master
Read
0
C_PLBV46_NUM_ Lock Error
MASTERS-1
Others
Unused, read as zero
Description
Master Lock Error.
Read: Lock error bit for each master
1 -error fields are locked (subsequent errors cannot
overwrite master's error fields until error is cleared)
0 - error fields are not locked (subsequent errors can
overwrite master's error fields)
Write: No effect.
Bus Error Address Registers
There are three PEAR registers. These registers contain the PLB address, PLB byte enables, PLB size, and PLB type
of the transaction that caused the error.
PEAR_ADDR: PLB Error Address Register
This register contains the low-order 32 bits of the PLB address of the transaction that caused the error as shown
Figure 11. This register is cleared when SYS_Rst is asserted or a 1 is written to the Software Reset bit.
The bit definitions for PEAR_ADDR are shown in Table 9.
Table 9: PLB PESR_LCK_ERR Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0 to 31 Bus Error
Read/Write 0 Bus Error Address, low bits
Address Low
Read: PLB address where error occurred.
Write: If the Test Enable bit is asserted in the PACR, this
field is writable. Otherwise, a write has no effect.
X-Ref Target - Figure 11
0
31
PLB Address Low
Figure 11: PEAR_ADDR Register
DS531_11_061608
PEAR_BYTE_EN: PLB Error Byte Enables and High-Order Address
This register contains on the left the values of the PLB byte enables and on the right the high-order address bits of
the transaction that caused the error as shown in Figure 12. The width of the PLB byte enable bus is the width of the
PLB data bus divided by 8. Therefore, if the PLB data bus is 128 bits wide, there are 16 byte enables. This register is
cleared when SYS_Rst is asserted or a 1 is written to the Software Reset bit.
DS531 September 21, 2010
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Product Specification