DS531 Datasheet, PDF (25/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Table 11: PLB PEAR_SIZE_TYPE Bit Definitions
Bit(s) Name Core Access Reset Value
Description
0 to 3 PLB Size
Read
Write⁽¹⁾
’0000’
PLB Size.
Read: PLB size value when error occurred
Write: If the if the Test Enable bit is asserted in the
PACR, this field is writable.Otherwise, a write has no
effect.
4 to 6 PLB Type
Read
Write⁽¹⁾
’00’
PLB Type.
Read: PLB type value when error occurred
Write: If the if the Test Enable bit is asserted in the
PACR, this field is writable.Otherwise, a write has no
effect.
Others Unused, read as zero
Notes:
1. This register can be written if the Test Enable bit is asserted in the PACR. Unused bits are not writable.
PLB Control Register
There is one PLB Control register that enables or disables the interrupt request output from the PLB and provides a
software reset.
PACR: PLB Control Register
This register contains one bit that enables or disables the interrupt request and another bit used to reset the PLB as
shown in Figure 14.
Note that the default state of the control register is to have interrupts enabled, therefore if the PLB is parameterized
to not have a DCR interface (C_DCR_INTFCE = 0) then interrupts are still enabled.
Also note that when the Software reset bit is asserted, ALL registers and flip-flops within the PLB including all
PEAR/PESR registers are reset. This reset occurs independent of the current PLB transaction state, therefore, this
reset should be used carefully.
This register is reset to the default state whenever SYS_Rst is asserted or a 1 is written to the Software Reset bit. The
bit definitions for PACR are shown in Table 12.
X-Ref Target - Figure 14
Test
Enable
Interrupt
Enable
0 123
Software
Reset
Unused
Figure 14: PACR (C_DCR_DWIDTH=32)
31
DS531_14_061608
DS531 September 21, 2010
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Product Specification