DS531 Datasheet, PDF (14/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Parameter/Port Dependencies
The width of many of the PLB signals depends on the number of PLB masters and number of PLB slaves in the
design. In addition, when certain features are parameterized away, the related input signals are unconnected and
the related output signals are set to constant values. The dependencies between the PLB design parameters and I/O
signals are shown in Table 4.
Table 4: Parameter-Port Dependencies
Generic
or Port
Name
Affects Depends
Relationship Description
Design Parameters
G1 C_PLBV46_NUM_ MASTERS P12-
P39P59,
P60 P61,
P74, P75,
P94
The width of many buses is set by the number of PLB
masters in the design.
G2 C_PLBV46_NUM_ SLAVES
P58 - P72
The width of many buses is set by the number of PLB
slaves in the design.
G3 C_PLBV46_AWIDTH
P13, P41
G4 C_PLBV46_DWIDTH
P14, P26,
P33, P42,
P56, P60,
P65, P74
G5 C_DCR_INTFCE
G6 - G9,
G15, P1-
P6
If C_P2P=1, then DCR interface is not available.
G6 C_BASEADDR
G5
Unconnected if C_DCR_INTFCE=0 or C_P2P=1.
G7 C_HIGHADDR
G5
Unconnected if C_DCR_INTFCE=0 or C_P2P=1.
G8 C_DCR_AWIDTH
P1
G5
Unconnected if C_DCR_INTFCE=0 or C_P2P=1.
G9 C_DCR_DWIDTH
P4, P6
G5
Unconnected if C_DCR_INTFCE=0 or C_P2P=1.
G10 C_IRQ_ACTIVE
P73
G11 C_EXT_RESET_ HIGH
G12 C_PLBV46_MID_ WIDTH
P46
G1
Master ID width is
log2(C_PLBV46_NUM_MASTERS).
G13 C_FAMILY
G15 C_P2P
G5-G9,
P1-P6
The DCR interface is available only in shared bus
configuration. The DCR parameters have no impact
and the DCR ports are unconnected if C_P2P = 1.
DS531 September 21, 2010
www.xilinx.com
14
Product Specification