DS531 Datasheet, PDF (8/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Table 2: PLB Design Parameters (Cont’d)
Generic
Feature /
Description
Parameter Name
Allowable Values
Default VHDL
Value
Type
System
G13 Target FPGA family C_FAMILY
spartan3, spartan3e,
spartan3a, spartan3adsp,
aspartan3, aspartan3e,
aspartan3a,
aspartan3adsp,spartan6,
virtex4, qvirtex4,
qvvirtex4, virtex5,
virtex5fx, virtex6,
virtex6cx
string
G14 Address pipelining
type supported
C_ADDR_
PIPELINING_TYPE
0 = no address pipelining
1 = 2-level address
pipelining
1
integer
G15 Optimize PLB for
C_P2P
point-to-point topology
(one master & one
slave)
0 = PLB is configured in a
shared bus mode
topology
0
integer
1 = PLB is configured with
one master and one slave
for point-to-point topology
G16 Selects the arbitration C_ARB_TYPE
scheme for all master
devices connected to
the bus.
0 = Fixed priority
1 = Round robin
0
integer
Notes:
1. The supported allowable values for the parameter, C_PLBV46_NUM_MASTERS, are 1 - 16. Only the values of 1 -
8 have been tested in a unit-level verification environment.
2. The supported allowable values for the parameter, C_PLBV46_NUM_SLAVES, are 1 - 16. Only the values of 1 - 8
have been tested in a unit-level verification environment.
3. The range specified by C_BASEADDR and C_HIGHADDR must comprise a complete, contiguous power of two
range such that range = 2ⁿ, and the n least significant bits of C_BASEADDR must be zero. To allow for the 8 DCR
registers within the PLB, n must be at least 3. Note that the DCR interface is only available in shared bus
configuration; it is not available in P2P configuration.
4. No default value is specified for C_BASEADDR or C_HIGHADDR to insure that the actual value is set. For example,
if the value is not set, a compiler error is generated.
5. The interrupt request output is generated as an edge type interrupt. A specific interrupt acknowledge response is
not required.
6. These parameters are automatically calculated by the system generation tool and are not input by the user.
Allowable Parameter Combinations
The address range specified by C_BASEADDR and C_HIGHADDR must comprise a complete, contiguous power
of two range such that range = 2ⁿ, and the n least significant bits of C_BASEADDR must be zero.
To allow for the registers in the PLB design, this range must be at least 7; therefore n must be at least 3. This means
that at a minimum, the three least significant bits of C_BASEADDR must be 0.
The base address and high address parameters determine the number of most significant address bits used to
decode the address space. These parameters allow the user to trade-off address space resolution with size and
speed of the PLB.
Some parameters can cause other parameters to be irrelevant. See Table 4 for information on the relationship
between design parameters.
DS531 September 21, 2010
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Product Specification