DS531 Datasheet, PDF (7/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
PLB Design Parameters
To allow for a PLB that is tailored to the target embedded system, certain features can be parameterized in the Xilinx
PLB. This allows the user to have a design that only utilizes the resources required by the system and runs at the
best possible performance. The features that can be parameterized in the Xilinx PLB are shown in Table 2.
Table 2: PLB Design Parameters
Generic
Feature /
Description
Parameter Name
Allowable Values
Default VHDL
Value
Type
PLB Features
G1 Number of PLB
Masters
C_PLBV46_NUM_
MASTERS
1 - 16⁽¹⁾
4
integer
G2 Number of PLB Slaves C_PLBV46_NUM_
SLAVES
1 - 16⁽²⁾
8
integer
G3 PLB Address Bus
Width
C_PLBV46_AWIDTH 32
32 integer
G4 PLB Data Bus Width C_PLBV46_DWIDTH 32, 64, 128
64 integer
G5 Include DCR interface C_DCR_INTFCE
1 = Include DCR slave
0
integer
interface; shared bus
configuration only
0 = DCR slave interface
not included; only allowed
value in P2P configuration
DCR Interface (Available only in a shared bus configuration)
G6 DCR Base Address C_BASEADDR
Valid DCR address⁽³⁾
None⁽⁴⁾ std_logic_
vector
G7 DCR High Address C_HIGHADDR
Valid DCR address
None std_logic_
vector
G8 DCR Address Bus
C_DCR_AWIDTH
10
Width
10 integer
G9 DCR Data Bus Width C_DCR_DWIDTH
32
32 integer
Interrupts
G10 Active Interrupt
State⁽⁵⁾
C_IRQ_ACTIVE
0 = interrupt request is
driven as a falling edge
1 = interrupt request is
driven as a rising edge
1
std_logic
System
G11 Active level of external C_EXT_RESET_
reset
HIGH
1 = external reset is active
high
0=external reset is active
low
1
integer
Auto-calculated parameters⁽⁶⁾
G12 Number of bits
C_PLBV46_MID_
required to encode the WIDTH
number of PLB
Masters
1-
2
integer
log2(C_PLBV46_NUM_M
ASTERS)
DS531 September 21, 2010
www.xilinx.com
7
Product Specification