DS531 Datasheet, PDF (15/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Table 4: Parameter-Port Dependencies (Cont’d)
Generic
or Port
Name
Affects Depends
Relationship Description
I/O Signals
P1 DCR_ABus[0:C_DCR_
AWIDTH-1]
G5, G8
Width varies with the size of the DCR address bus.
This input is unconnected if C_DCR_INTFCE=0 or
C_P2P = 1.
P2 DCR_Read
G5
This input is unconnected if C_DCR_INTFCE=0 or
C_P2P = 1.
P3 DCR_Write
G5
This input is unconnected if C_DCR_INTFCE=0 or
C_P2P = 1.
P4 DCR_DBus[0:C_DCR_
DWIDTH-1]
G5, G9
Width varies with the size of the DCR data bus.
This input is unconnected if C_DCR_INTFCE=0 or
C_P2P = 1.
P5 PLB_dcrAck
G5
This output is grounded if C_DCR_INTFCE=0 or
C_P2P = 1.
P6 PLB_dcrDBus[0:C_DCR_
DWIDTH-1]
G5, G9
Width varies with the size of the DCR data bus.
This output is grounded if C_DCR_INTFCE=0 or
C_P2P = 1.
P7 PLB_rdPendPri[0:1]
P8 PLB_wrPendPri[0:1]
P9 PLB_rdPendReq
P10 PLB_wrPendReq
P11 PLB_reqPri[0:1]
P12 M_abort[0:C_PLBV46_NUM_
MASTERS-1]
G1
Width varies with the number of PLB masters.
P13 M_ABus[0:C_PLBV46_NUM_
MASTERS*32-1]
G1, G3 Width varies with the size of the PLB address bus
and the number of PLB masters.
P14 M_BE[0:C_PLBV46_NUM_
MASTERS*C_PLBV46_
DWIDTH/8-1]
G1,G4 Width varies with the size of the PLB data bus and
the number of PLB masters.
P15 M_busLock[0:C_PLBV46_NUM
_MASTERS-1]
G1
Width varies with the number of PLB masters.
P16 M_TAttribute[0:16*C_PLBV46_
NUM_MASTERS-1]
G1
Width varies with the number of PLB masters.
P17 M_lockErr[0:C_PLBV46_NUM_
MASTERS-1]
G1
Width varies with the number of PLB masters.
P18 M_mSize[0:C_PLBV46_NUM_
MASTERS*2 -1]
G1
Width varies with the number of PLB masters.
P19 M_priority[0:C_PLBV46_NUM_
MASTERS*2 -1]
G1, G17 Width varies with the number of PLB masters. When
C_ARB_TYPE = 1, the M_priority bits are ignored.
P20 M_rdBurst[0:C_PLBV46_NUM_
MASTERS-1]
G1
Width varies with the number of PLB masters.
P21 M_request[0:C_PLBV46_NUM_
MASTERS-1]
G1
Width varies with the number of PLB masters.
P22 M_RNW[0:C_PLBV46_NUM_
MASTERS-1]
G1
Width varies with the number of PLB masters.
DS531 September 21, 2010
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15
Product Specification