DS531 Datasheet, PDF (20/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
PLB Error Status Registers
There are four PESR registers that provide error information - was an error detected, which Master’s errant address
and byte enables are in the PEARs, was the error due to a read or write transaction, and did the master lock the error
condition. If a read of the PESR_MERR_DETECT register returns all zeros, then no masters detected any errors and
no further reads are necessary.
PESR_MERR_DETECT: Master Error Detect Bits
This register contains the error detect bit for each master. The bit location corresponds to the PLB Master. For
example, if PLB Master 0 has experienced an error, then bit 0 is set. Writing a 1 to a bit in this register clears this bit
and the corresponding bit in the other PESRs (PESR_MDRIVE_PEAR, PESR_RNW_ERR, and PESR_LCK_ERR).
If a particular master experienced an error and had locked the PEARs⁽¹⁾, writing a 1 to the corresponding bit in this
register would clear and unlock the error fields of the master and unlock the PEARs. The bits in this register are
reset when a 1 has been written to the register, SYS_Rst has been asserted, or a 1 has been written to the Software
Reset bit in the PACR. Figure 7 shows the bit definitions of this register when the number of PLB masters is 8.
The bit definitions for PESR_MERR_DETECT are shown in Table 6. The bits is this register are reset by writing a 1
to the bit.
X-Ref Target - Figure 7
M2
M6
Error
Error
M0 _Detect M4 _Detect
Error
Error
Detect
Detect
0 1234 56 7 8
31
M1
M5
Error
Error
Detect ^M3 Detect ^M7
Error
Error
Detect
Detect
Unused
DS531_07_061608
Figure 7: PESR_MERR_DETECT (C_PLBV46_NUM_MASTERS=8, C_DCR_DWIDTH=32)
Table 6: PLB PESR_MERR_DETECT Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
0 toC_PLBV46_NUM_ Master
Read/Write
0
Master Error Detect.
MASTERS-1
Error
Detect
Read: Error detect bit for PLB Masters 0 to
C_PLBV46_NUM_ MASTERS-1 respectively.
1 - error detected
0 - no error detected
Write: Clear error bit for PLB Masters 0 to
C_PLBV46_NUM_ MASTERS -1 respectively.
1 - clear and unlock corresponding master’s error
fields and PESRs
0 - do not clear error
Others
Unused, read as zero
1. A master specifies whether errors are to be locked on a transaction-by-transaction basis by asserting the M_lockErr qualifier signal.
DS531 September 21, 2010
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Product Specification