DS531 Datasheet, PDF (6/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Slave devices supporting address pipelining must be able to assert either Sl_reArbitrate or Sl_addrAck to the
PLB_SAValid transaction. The PLB_SAValid operation cannot time out by the arbiter, only the primary
transaction, indicated by the assertion of PLB_PAValid. Figure 6 illustrates an example of PLB_SAValid asserted
for more than the primary transaction time out count value. The arbiter will not time out the PLB_SAValid
transaction, but will wait for the promotion of PLB_SAValid to PLB_PAValid (indicated by Sl_rdComp), then
the time out counter will be activated. If during the assertion of PLB_PAValid neither Sl_reArbitrate or
Sl_addrAck is asserted, the PLB_MTimeout will be asserted after 16 clock cycles.
X-Ref Target - Figure 6
PLB_Clk
M_Request
M_RNW
PLB_PAValid
1
2
PLB_SAValid
2
PLB_RNW
PLB_rdPrim
PLB_wrPrim
Sl_addrAck
1
Sl_reArbitrate
Sl_rdComp
1
Sl_wrComp
Sl_wait
PLB_MTimeout
2
DS531_06_061608
Figure 6: Timeout Only on Promotion of Secondary to Primary Transaction
DS531 September 21, 2010
www.xilinx.com
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Product Specification