DS531 Datasheet, PDF (21/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
PESR_MDRIVE_PEAR: Master Driving PEAR
This register indicates which PLB Master is driving the PEARs. Each bit location in this register corresponds to a
PLB Master. For example, if PLB Master 0 is driving the PEARs, then bit 0 is set. Only one master can drive the
PEARs, therefore, only one bit is set in this register. Writing to this register has no effect. The bits in this register are
reset when a 1 is written to the corresponding bits in PESR_MERR_DETECT, SYS_Rst has been asserted, or a 1 has
been written to the Software Reset bit in the PACR. Figure 8 shows the bit definitions of this register when the
number of PLB masters is 8 and the width of the DCR data bus is 32.
The bit definitions for PESR_MDRIVE_PEAR are shown in Table Notes:.
X-Ref Target - Figure 8
M2
M6
Driving
Driving
M0 _PEAR M4 _PEAR
Driving
Driving
PEAR
PEAR
0 1234 56 7 8
31
M1
M5
Driving
Driving
PEAR ^M3 PEAR ^M7
Driving
Driving
PEAR
PEAR
Unused
DS531_08_061608
Figure 8: PESR_MDRIVE_PEAR (C_PLBV46_NUM_MASTERS=8, C_DCR_DWIDTH=32)
Notes: PLB PESR_MDRIVE_PEAR Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
0 to C_PLBV46_NUM_ Master
Read
0
MASTERS-1
Driving
PEAR
Others
Unused, read as zero
Description
Master Driving PEAR.
Read: PEAR bit for PLB Masters 0 to
C_PLBV46_NUM_ MASTERS-1 respectively.
1 - master is driving PEAR
0 - master is not driving PEAR
Write: No effect.
PESR_RNW_ERR: Master Read/Write Bits
This register indicates the read/write condition that caused the error for each PLB Master. Each bit location in this
register corresponds to a PLB Master. For example, if PLB Master 0 experienced an error during a read operation, bit
0 would be set.
If PLB Master 1 experienced an error during a write operation, bit 1 would be reset. Writing to this register has no
effect. The bits in this register are reset when a 1 is written to the corresponding bits in PESR_MERR_DETECT,
SYS_Rst has been asserted, or a 1 has been written to the Software Reset bit in the PACR. Figure 9 shows the bit
definitions of this register when the number of PLB masters is 8 and the width of the DCR data bus is 32.
DS531 September 21, 2010
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Product Specification