DS531 Datasheet, PDF (1/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

DS531 September 21, 2010
LogiCORE IP Processor
Local Bus
(PLB) v4.6 (v1.05a)
Product Specification
Introduction
The Xilinx 128-bit Processor Local Bus (PLB) v4.6
provides bus infrastructure for connecting an optional
number of PLB masters and slaves into an overall PLB
system. It consists of a bus control unit, a watchdog
timer, and separate address, write, and read data path
units, as well as an optional DCR (Device Control
Register) slave interface to provide access to its bus
error status registers.
Features
• Arbitration support for a configurable number of
PLB master devices
• PLB address and data steering support for all
masters
• 128-bit, 64-bit, and 32-bit support for masters and
slaves
• PLB address pipelining (supported in shared bus
mode or point-to-point configuration)
• Three-cycle arbitration
• Four levels of dynamic master request priority
• Selectable round robin or fixed priority arbitration
• Configurable optimization for point-to-point
topology
• PLB watchdog timer
• PLB architecture compatible
• Complete PLB bus structure provided
• Supports a configurable number of slave
devices
• No external OR gates required for PLB slave
input signals
• PLB Reset circuit
• PLB Reset generated synchronously to the PLB
clock
• PLB Reset generated synchronously from
external reset when external reset provided
• Provides vectorized reset signal to reduce
system fanout for improved timing
• Active state of external reset selectable via a
design parameter
LogiCORE™ IP Facts
Core Specifics
Supported Device
Family
Spartan®-3E, Automotive
Spartan 3/3E/3A/3A DSP, Spartan-6,
Virtex®-4 /4Q/4QV, Virtex-5/5FX,
Virtex-6/6C
Version of Core plb_v46
v1.05a
Resources Used See Table 13, page 34.
Provided with Core
Documentation Product Specification
Design File
Formats
VHDL
Constraints File N/A
Verification
N/A
Instantiation
Template
N/A
Design Tool Requirements
Xilinx
Implementation
Tools
ISE® v12.3 or later
Verification
Mentor Graphics ModelSim: v6.5c
Simulation
Mentor Graphics ModelSim: v6.5c
Synthesis
XST
Support
Provided by Xilinx, Inc.
© Copyright 2008-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United
States and other countries. All other trademarks are the property of their respective owners.
DS531 September 21, 2010
www.xilinx.com
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Product Specification