DS531 Datasheet, PDF (2/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Functional Description
The Xilinx PLB consists of a central bus arbiter, the necessary bus control and gating logic, and all necessary bus
OR/MUX structures. The Xilinx PLB provides the entire PLB bus structure and allows for direct connection with a
configuration number of masters and slaves. Figure 1 provides an example of the PLB connections for a system with
three masters and three slaves.
X-Ref Target - Figure 1
Shared Bus
Arbitration
Address and
Transfer Qualifiers
Write Data Bus
Control
Central Bus Arbiter
Bus Control &
Gating Logic
Address and
Transfer Qualifiers
Write Data Bus
Control
Read Data Bus
Status & Control
Read Data Bus
Status & Control
PLB Masters
PLB Core
Figure 1: PLB Interconnect Diagram
PLB Slaves
DS531_01_061608
Basic Operation
The Xilinx PLB has three-cycle arbitration during the address phase of the transaction as shown in Figure 2. There
is a two-cycle delay from Mn_request to PLB_PAValid. If the slave can respond combinatorially in the same
cycle—the optimistic assumption shown and theoretically possible for a write transaction—the whole transaction
takes three cycles.
The two-cycle delay from Mn_request to PLB_PAValid holds for the case where there are two or more attached
masters and allows one cycle for a priority arbitration to occur and one cycle to route the selected master’s
transaction data and qualifiers to the slaves. If there is a single master, arbitration is not necessary and transaction
data and qualifiers can be driven to the slaves without multiplexing. This allows PLB_PAValid to be driven after
one clock, saving a cycle of latency.
DS531 September 21, 2010
www.xilinx.com
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Product Specification