DS531 Datasheet, PDF (27/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
PLB Block Diagram
Figure 15 provides a comprehensive block diagram of the PLB.
X-Ref Target - Figure 15
Master Slave
Ports Ports
Master Slave
Ports Ports
Master
Ports
Slave
Ports
Address Path
Write Data Path
Read Data Path
DCR Bus Interface
Master Ports
Bus Control Unit
Watchdog Timer _{Slave Ports}
Sys_Rst
PLB_Clk
Reset Logic
PLB_Rst
SPLB_Rst
MPLB_Rst
Figure 15: PLB Block Diagram
DS531_15_061608
Address Path Unit
The PLB address path unit contains the muxing needed to select the master address which is driven to the slave
devices on the PLB address output.
Write Data Path Unit
The PLB write data path unit contains the steering logic needed for the master and slave write data buses.
Read Data Path Unit
The PLB read data path unit contains the steering logic needed for the master and slave read data buses.
Bus Control Unit
The PLB bus control unit consists of a bus arbitration control unit that manages the address and data flow through
the PLB and DCRs. The bus arbitration control unit supports arbitration for 16 PLB masters. The address and data
flow control logic provides address pipelining and address and data steering support for 16 PLB masters and 8 PLB
slaves.
DCR-accessible, PLB registers may be optioned in for use in reporting timeout errors if the bus is configured as a
shared bus. The registers are accessed by using the move from device control register (mfdcr) and move to device control
register (mtdcr) instructions, which move data between the device control registers and the processor’s general
purpose registers.
See the "PLB Registers" section for additional information.
DS531 September 21, 2010
www.xilinx.com
27
Product Specification