DS531 Datasheet, PDF (30/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Master[n] Interface
Figure 17 shows all master[n] interface I/O signals (where n is the number of a master 0 to C_PLBV46_NUM_
MASTERS-1). See the IBM 128-Bit Processor Local Bus Architectural Specification (v4.6) for detailed functional
descriptions of these signals. Note that C_PLBV46_DWIDTH =128 and C_PLBV46_AWIDTH=36 in this diagram.
X-Ref Target - Figure 17
PLB
Core
Clk
MPLB_Rst[n]
PLB_MAddrAck[n]
PLB_MRearbitrate
PLB_MSize[n*2:n+1]
PLB_MBusy[n]
PLB_MRdErr[n], PLB_WrErr[n]
PLB_rdPendReq, PLB_wrPendReq
PLB_rdPendPri[0:1], PLB_wrPendPri[0:1]
PLB_reqPri[0:1]
PLB_MTimeout
PLB_MIRQ
M_request[n]
M_priority[n*:n*2+1]
M_buslock[n]
M_RNW[n]
M_BE[n*16:n*16+15]
M_size[n*4:n*4+3]
M_type[n*3:n*3+2]
M_MSize[n*2:2+1]
M_TAttribute[n]
M_lockErr[n]
M_abort[n]
M_UABusin[n*4:n*4+3], M_ABusin[n*32:n*32+31]
PLB_MWrDAck[n]
PLB_MWrBTerm[n]
M_wrBurst[n]
M_WrDBus[n*128:n*128+127]
PLB_MRdDAck[n]
PLB_MRdBTerm[n]
PLB_MRdWdAddr[n*:4:n*4+3]
PLB_MRdDBusin[n*128:n*128+`27]
M_rdBurst[n]
Master[n]
Interface
Figure 17: Master[n] Interface
DS531_17_061608
DS531 September 21, 2010
www.xilinx.com
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Product Specification