DS531 Datasheet, PDF (17/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Table 4: Parameter-Port Dependencies (Cont’d)
Generic
or Port
Name
Affects
P46 PLB_masterID[0:C_PLBV46_MI
D_ WIDTH-1]
P47 PLB_MSize[0:1]
P48 PLB_PAValid
P49 PLB_rdBurst
P50 PLB_rdPrim[0:C_PLBV46_NUM
_ SLAVES-
1][0:C_PLBV46_NUM_
SLAVES-1]
P51 PLB_RNW
P52 PLB_SAValid
P53 PLB_size[0:3]
P54 PLB_type[0:2]
P55 PLB_wrBurst
P56 PLB_wrDBus[0:C_PLBV46_
DWIDTH-1]
P57 PLB_wrPrim[0:C_PLBV46_NU
M_ SLAVES-
1][0:C_PLBV46_NUM_
SLAVES-1]
P58 Sl_addrAck[0:C_PLBV46_NUM
_ SLAVES-1]
P59 Sl_MRdErr[0:C_PLBV46_NUM
_ SLAVES*C_PLBV46_NUM_
MASTERS-1]
P60 Sl_MWrErr[0:C_PLBV46_NUM
_ SLAVES*C_PLBV46_NUM_
MASTERS-1]
P61 Sl_MBusy[0:C_PLBV46_NUM_
SLAVES*C_PLBV46_NUM_
MASTERS-1]
P62 Sl_rdBTerm[0:C_PLBV46_NUM
_ SLAVES-1]
P63 Sl_rdComp[0:C_PLBV46_NUM
_ SLAVES-1]
P64 Sl_rdDAck[0:C_PLBV46_NUM_
SLAVES-1]
P65 Sl_rdDBus[0:C_PLBV46_NUM_
SLAVES*C_PLBV46_ DWIDTH-
1]
P66 Sl_rdWdAddr[0:C_PLBV46_NU
M_ SLAVES*4-1]
P67 Sl_rearbitrate[0:C_PLBV46_NU
M_ SLAVES-1]
Depends
Relationship Description
G12 Width varies with the number of PLB masters.
Width varies with the number of PLB slaves.
G4
Width varies with the size of the PLB data bus.
Width varies with the number of PLB slaves.
G2
Width varies with the number of PLB slaves.
G1, G2 Width varies with the number of PLB slaves and the
number of PLB masters.
G1, G2 Width varies with the number of PLB slaves and the
number of PLB masters.
G1, G2 Width varies with the number of PLB slaves and the
number of PLB masters.
G2
Width varies with the number of PLB slaves.
G2
Width varies with the number of PLB slaves.
G2
Width varies with the number of PLB slaves.
G2,G3 Width varies with the number of PLB slaves and the
size of the PLB data bus.
G2
Width varies with the number of PLB slaves.
G2
Width varies with the number of PLB slaves.
DS531 September 21, 2010
www.xilinx.com
17
Product Specification