DS531 Datasheet, PDF (26/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Table 12: PLB PACR Bit Definitions
Bit(s)
Name Core Access
0
Interrupt Read/Write
Enable
1
Software Read/Write
Reset ⁽¹⁾
2
Test Enable Read/Write
3 to
Unused, read as zero
C_DCR_DWIDTH-1
Reset
Value
1
0
0
Description
Interrupt Enable.
Read: PLB Interrupt Enable
Write:
1 - enable interrupts
0 - disable interrupts
Software Reset.
Read: This bit will always read 0 because it
is reset whenever a 1 is written to it.
Write:
1 - reset the PLB
0 - resume normal PLB operation
Test Enable.
Read: Test Enable
Write:
1 - Enable writing to the PEAR registers
0 - PEAR registers are not writable
Notes:
1. Use the software reset cautiously because the software reset will reset the entire PLB regardless of the current PLB
transaction state.
PLB Interrupt Description
The PLB has one interrupt request output called Bus_Error_Det. The interrupt is signaled when a bus transfer
times out because it is not responded to by any slave. This interrupt is an edge type interrupt and is automatically
reset to the inactive state on the next clock cycle, therefore an explicit interrupt acknowledge is not required. The
active level of the Bus_Error_Det interrupt is determined by the design parameter, C_IRQ_ACTIVE.
Note that if interrupts are enabled, then an interrupt request from the PLB is generated whenever any time out error
is detected regardless of whether masters have locked their error fields or not. See "PLB Registers," page 19. If the
parameter C_DCR_INTFCE is 0, which indicates that there is no DCR interface, interrupts will remain enabled
because the default state of the Interrupt Enable bit in the PACR is asserted.
Master Interrupt Request
The Xilinx PLB supports the Sl_MIRQ (0 to C_PLBV46_NUM_ SLAVES*C_PLBV46_NUM_ MASTERS - 1) signal,
which allows each slave to signal to any master that it has encountered an event that it considers important to that
master. The only function of the Xilinx PLB with respect to the MIRQ signals is to OR all the Sl_MIRQ signals for a
given master into the corresponding bit of PLB_MIRQ(0 to C_PLBV46_NUM_ MASTERS-1).
DS531 September 21, 2010
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Product Specification