DS531 Datasheet, PDF (22/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
.
X-Ref Target - Figure 9
M0 ^M2 M4 ^M6
RNW ^RNW RNW ^RNW
01234 56 7 8
31
M1 M3 M5 M7
RNW RNW RNW RNW
Unused
DS531_09_061608
Figure 9: PESR_RNW_ERR (C_PLBV46_NUM_MASTERS=8, C_DCR_DWIDTH=32)
The bit definitions for PESR_RNW_ERR are shown in Table 7.
Table 7: PLB PESR_RNW_ERR Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
0 to
Master Read
Read
0
C_PLBV46_NUM_
Not Write
MASTERS-1
Others
Unused, read as zero
Description
Master Read Not Write.
Read: RNW status for each master
1 - error was in response to a read
0 - error was in response to a write
Write: No effect.
PESR_LCK_ERR: Master Lock Error Bits
This register indicates whether each PLB Master has locked their error bits. Each bit location in this register
corresponds to a PLB Master. Setting the Master’s lock error bit means that the error fields of the master are locked,
which means that subsequent errors cannot overwrite master's error fields until error is cleared.
If the Master’s lock error bit is reset, the master’s error fields are not locked and subsequent errors will overwrite the
master’s error fields. Writing to this register has no effect. The bits in this register are reset when a 1 is written to the
corresponding bits in PESR_MERR_DETECT, SYS_Rst has been asserted, or a 1 has been written to the Software
Reset bit in the PACR. Figure 10 shows the bit definitions of this register when the number of PLB masters is 8 and
the width of the DCR data bus is 32. The bit definitions for PESR_LCK_ERR are shown in Table 8.
X-Ref Target - Figure 10
M0 M2 M4 M6
Lock Lock Lock Lock
Error Error Error Error
0 1234 56 7 8
31
M1 _M3 M5 _M7
Lock _Lock Lock _Lock
Error _Error Error _Error
Unused
DS531_10_061608
Figure 10: PESR_LCK_ERR (C_PLBV46_NUM_MASTERS=8, C_DCR_DWIDTH=32)
DS531 September 21, 2010
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Product Specification