English
Language : 

XC4VLX100-11FF1148C Datasheet, PDF (8/58 Pages) Xilinx, Inc – DC and Switching Characteristics
◁
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
SelectIO™ DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for IOL and IOH are guaranteed over the recom-
mended operating conditions at the VOL and VOH test
points. Only selected standards are tested. These are cho-
sen to ensure that all standards meet their specifications.
The selected standards are tested at a minimum VCCO with
the respective VOL and VOH voltage levels shown. Other
standards are sample tested.
Table 7: SelectIO DC Input and Output Levels
IOSTANDARD
Attribute
V, Min
VIL
V, Max
VIH
V, Min
V, Max
VOL
V, Max
VOH
V, Min
IOL
IOH
mA mA
LVTTL
–0.2
0.8
2.0
3.45
0.4
2.4
Note(3) Note(3)
LVCMOS33,
LVDCI33
–0.2
0.8
2.0
3.45
0.4
VCCO – 0.4 Note(3) Note(3)
LVCMOS25,
LVDCI25
–0.3
0.7
1.7
VCCO + 0.3
0.4
VCCO – 0.4 Note(3) Note(3)
LVCMOS18,
LVDCI18
–0.3
35% VCCO
65% VCCO VCCO + 0.3
0.4
VCCO – 0.45 Note(4) Note(4)
LVCMOS15,
LVDCI15
–0.3
35% VCCO
65% VCCO VCCO + 0.3
0.4
VCCO – 0.45 Note(4) Note(4)
PCI33_3(5)
PCI66_3(5)
PCI-X(5)
–0.2
–0.2
–0.2
30% VCCO
30% VCCO
35% VCCO
50% VCCO
50% VCCO
50% VCCO
VCCO
10% VCCO 90% VCCO
1.5
VCCO
10% VCCO 90% VCCO
1.5
VCCO
10% VCCO 90% VCCO
1.5
GTLP
–0.3
VREF – 0.1
VREF + 0.1
–
0.6
N/A
36
GTL
HSTL I(2)
–0.3 VREF – 0.05 VREF + 0.05
–
0.4
–0.3
VREF – 0.1
VREF + 0.1 VCCO + 0.3
0.4
N/A
32
VCCO – 0.4
8
HSTL II(2)
–0.3
VREF – 0.1
VREF + 0.1 VCCO + 0.3
0.4
VCCO – 0.4
16
HSTL III(2)
HSTL IV(2)
–0.3
VREF – 0.1
VREF + 0.1 VCCO + 0.3
0.4
–0.3
VREF – 0.1
VREF + 0.1 VCCO + 0.3
0.4
VCCO – 0.4
24
VCCO – 0.4
48
DIFF HSTL II(2)
–0.3
50%
VCCO – 0.1
50%
VCCO + 0.1
VCCO + 0.3
0.4
VCCO – 0.4
–
SSTL2 I
–0.3 VREF – 0.15 VREF + 0.15 VCCO + 0.3 VTT – 0.61 VTT + 0.61
8.1
SSTL2 II
–0.3 VREF – 0.15 VREF + 0.15 VCCO + 0.3 VTT – 0.81 VTT + 0.81 16.2
DIFF SSTL2 II
–0.3
50%
VCCO – 0.15
50%
VCCO + 0.15
VCCO + 0.3
0.5
VCCO – 0.5
–
SSTL18 I
–0.3 VREF – 0.125 VREF + 0.125 VCCO + 0.3 VTT – 0.47 VTT + 0.47
6.7
SSTL18 II
–0.3 VREF – 0.125 VREF + 0.125 VCCO + 0.3 VTT – 0.60 VTT + 0.60 13.4
DIFF SSTL18 II
–0.3
50%
VCCO – 0.125
50%
VCCO + 0.125
VCCO + 0.3
0.4
VCCO – 0.4
–
Notes:
1. Tested according to relevant specifications.
2. Applies to both 1.5V and 1.8V HSTL.
3. LVCMOS using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
4. LVCMOS using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
5. For more information on PCI33_3, PCI66_3, and PCI-X, refer to the Virtex-4 FPGA User Guide, SelectIO Resources, Chapter 6.
–0.5
–0.5
–0.5
N/A
N/A
–8
–16
–8
–8
–
–8.1
–16.2
–
–6.7
–13.4
–
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
8
 ▷