XC4VLX100-11FF1148C Datasheet, PDF (26/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Input/Output Logic Switching Characteristics
Table 32: ILOGIC Switching Characteristics
Symbol
Setup/Hold
Description
T_ICE1CK / T_ICKCE1 CE1 pin Setup/Hold with respect to CLK
T_ICECK / T_ICKCE
DLYCE pin Setup/Hold with respect to C
T_IRSTCK / T_ICKRST DLYRST pin Setup/Hold with respect to C
T_IINCCK / T_ICKINC DLYINC pin Setup/Hold with respect to C
T_ISRCK / T_ICKSR
SR/REV pin Setup/Hold with respect to CLK
T_IDOCK / T_IOCKD
D pin Setup/Hold with respect to CLK without Delay
T_IDOCKD / T_IOCKDD
D pin Setup/Hold with respect to CLK
(IOBDELAY_TYPE = DEFAULT)
D pin Setup/Hold with respect to CLK
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)⁽¹⁾
Combinatorial
T_IDI
T_IDID
D pin to O pin propagation delay, no Delay
D pin to O pin propagation delay
(IOBDELAY_TYPE = DEFAULT)
D pin to O pin propagation delay
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)⁽¹⁾
Sequential Delays
T_IDLO
T_IDLOD
D pin to Q1 pin using flip-flop as a latch without Delay
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = DEFAULT)
D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)⁽¹⁾
T_ICKQ
T_ICE1Q
T_RQ
T_GSRQ
Set/Reset
CLK to Q outputs
CE1 pin to Q1 using flip-flop as a latch, propagation delay
SR/REV pin to OQ/TQ out
Global Set/Reset to Q outputs
T_RPW
Minimum Pulse Width, SR/REV inputs
Notes:
1. Recorded at 0 tap value. Refer to Timing Report for other values.
Speed Grade
-12
-11
-10
Units
0.58
–0.23
0.66
–0.23
0.79
–0.23
ns
0.16
0.11
0.19
0.13
0.23
0.16
ns
–0.03
0.37
–0.02
0.45
–0.02
0.54
ns
0.01
0.36
0.01
0.43
0.01
0.51
ns
1.15
–0.56
1.33
–0.56
1.59
–0.56
ns
0.24
–0.10
0.28
–0.10
0.34
–0.10
ns
6.64
–5.99
7.63
–5.99
8.84
–5.99
ns
0.81
–0.63
0.87
–0.63
1.09
–0.63
ns
0.17
0.20
0.24
ns
6.00
6.91
7.96
ns
0.74
0.79
0.99
ns
0.50
0.59
0.71
ns
6.90
7.94
9.21
ns
1.07
1.18
1.45
ns
0.53
0.60
0.72
ns
0.90
1.06
1.27
ns
1.70
2.03
2.44
ns
1.54
1.73
2.03
ns
0.53
0.59
0.70
ns,
Min
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
26