XC4VLX100-11FF1148C Datasheet, PDF (32/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
)
Table 38: CLB Distributed RAM Switching Characteristics
Speed Grade
-12
-11 -10
Symbol
Description
XC4VFX⁽²⁾ XC4VLX/SX ALL DEVICES Units
Sequential Delays
T_SHCKO
Clock CLK to X outputs (WE active)⁽³⁾
T_SHCKOF5
Clock CLK to F5 output (WE active)
Setup and Hold Times Before/After Clock CLK
1.61
1.58
1.77 2.08 ns, Max
1.53
1.50
1.69 1.98 ns, Max
T_DS / T_DH
BX/BY data inputs (DI)
1.26
–0.90
1.23
–0.88
1.46
–0.88
1.80
–0.88
ns, Min
T_AS / T_AH
F/G address inputs
0.88
–0.37
0.86
–0.37
0.97
–0.34
1.13
–0.29
ns, Min
T_WS / T_WH
WE input (SR)
1.10
–0.48
1.08
–0.47
1.21
–0.47
1.42
–0.47
ns, Min
Clock CLK
T_WPH
T_WPL
T_WC
Minimum Pulse Width, High
0.53
Minimum Pulse Width, Low
0.55
Minimum clock period to meet address write cycle time
0.76
0.52
0.59 0.69 ns, Min
0.54
0.60 0.70 ns, Min
0.74
0.84 0.98 ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent
XC4VLX/SX -12 column.
3. T_SHCKO also represents the CLK to XMUX output. Refer to TRCE report for the CLK to XMUX path.
CLB Shift Register Switching Characteristics (SLICEM Only)
)
Table 39: CLB Shift Register Switching Characteristics
Speed Grade
-12
-11
-10
Symbol
Description
XC4VFX⁽²⁾ XC4VLX/SX XC4VFX⁽³⁾ XC4VLX/SX ALL Units
Sequential Delays
T_REG
Clock CLK to X/Y outputs
T_REGXB
Clock CLK to XB output via MC15 LUT output
T_REGYB
Clock CLK to YB output via MC15 LUT output
T_CKSH
Clock CLK to Shiftout
T_REGF5
Clock CLK to F5 output
Setup and Hold Times Before/After Clock CLK
2.12
1.83
1.84
1.70
2.05
2.08
1.73
1.74
1.60
2.01
2.19
1.90
1.92
1.76
2.11
2.19
2.57 ns, Max
1.84
2.16 ns, Max
1.85
2.17 ns, Max
1.70
1.99 ns, Max
2.11
2.47 ns, Max
T_WS / T_WH WE input (SR)
0.87
–0.76
0.85
–0.76
0.96
–0.70
0.96
–0.70
1.12
–0.62
ns, Min
T_DS / T_DH BX/BY data inputs (DI)
1.28
–1.12
1.25
–1.11
1.45
–1.11
1.45
–1.11
1.75
–1.11
ns, Min
Clock CLK
T_WPH
Minimum Pulse Width, High
0.53
0.52
0.59
0.59
0.69 ns, Min
T_WPL
Minimum Pulse Width, Low
0.55
0.54
0.60
0.60
0.70 ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent
XC4VLX/SX -12 column.
3. The values in this column apply to all XC4VFX -11 parts.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
32