XC4VLX100-11FF1148C Datasheet, PDF (36/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Configuration Switching Characteristics
Table 43: Configuration Switching Characteristics
Speed Grade
Symbol
Description
-12
-11
-10
Units
Power-up Timing Characteristics
T_CONFIG(1,2)
T_PL
Maximum time to configure device after
V_CCINT has been applied.
Program Latency
10
10
10
minutes
0.5
0.5
0.5
µs/frame,
Max
T_POR
Power-on-Reset
T_ICCK
CCLK (output) delay
T_PROGRAM
Program Pulse Width
Master/Slave Serial Mode Programming Switching
T_PL + 10 T_PL + 10 T_PL + 10
500
500
500
300
300
300
ms, Max
ns, Min
ns, Min
T_DCC / T_CCD
DIN Setup/Hold, slave mode
0.5
1.0
0.5
1.0
0.5
1.0
ns, Min
T_DSCK / T_SCKD
DIN Setup/Hold, master mode
0.5
1.0
0.5
1.0
0.5
1.0
ns, Min
T_CCO
T_CCH
T_CCL
F_{CC_SERIAL}
DOUT
High Time
Low Time
Maximum Frequency, master mode with
respect to nominal CCLK.
7.5
7.5
7.5
ns, Max
2.0
2.0
2.0
ns, Min
2.0
2.0
2.0
ns, Min
100
100
100 MHz, Max
F_{MAX_SLAVE} / F_{MAX_ICAP}
Maximum Frequency, slave mode external
CCLK
100
100
100 MHz, Max
F_MCCTOL
Frequency Tolerance, master mode with
respect to nominal CCLK.
±50
±50
±50
%
SelectMAP Mode Programming Switching
T_SMDCC / T_SMCCD
SelectMAP Data Setup/Hold
2.0
0.0
2.0
0.0
2.0
0.0
ns, Min
T_SMCSCC / T_SMCCCS
CS_B Setup/Hold
1.0
0.5
1.0
0.5
1.0
0.5
ns, Min
T_SMCCW / T_SMWCC
RDWR_B Setup/Hold
6.0
1.0
6.0
1.0
6.0
1.0
ns, Min
T_SMCKBY
F_{CC_SELECTMAP}
BUSY Propagation Delay
Maximum Frequency, master mode with
respect to nominal CCLK.
8.0
8.0
8.0
ns, Max
100
100
100 MHz, Max
F_{MAX_SELECTMAP}
Maximum Configuration Frequency, slave
mode external CCLK
100
100
100 MHz, Max
F_{MAX_READBACK}
F_MCCTOL
Maximum Readback Frequency
Frequency Tolerance, master mode with
respect to nominal CCLK.
80
80
80
MHz, Max
±50
±50
±50
%
T_SMCO
SelectMAP Readback Clock-to-Out
8.0
8.0
8.0
ns, Max
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
36