XC4VLX100-11FF1148C Datasheet, PDF (28/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 34: ISERDES Switching Characteristics
Symbol
Setup/Hold for Control Lines
T_{ISCCK_BITSLIP} / T_{ISCKC_BITSLIP}
Description
BITSLIP pin Setup/Hold with respect to CLKDIV
T_{ISCCK_CE} / T_{ISCKC_CE(2)}
CE pin Setup/Hold with respect to CLK (for CE1)
T_{ISCCK_CE2} / T_{ISCKC_CE2(2)}
CE pin Setup/Hold with respect to CLKDIV (for CE2)
T_{ISCCK_DLYCE} / T_{ISCKC_DLYCE}
DLYCE pin Setup/Hold with respect to CLKDIV
T_{ISCCK_DLYINC} / T_{ISCKC_DLYINC}
DLYINC pin Setup/Hold with respect to CLKDIV
T_{ISCCK_DLYRST} / T_{ISCKC_DLYRST} DLYRST pin Setup/Hold with respect to CLKDIV
T_{ISCCK_SR}
Setup/Hold for Data Lines
SR pin Setup with respect to CLKDIV
D pin Setup/Hold with respect to CLK
(IOBDELAY = IBUF or NONE)
T_{ISDCK_D} / T_{ISCKD_D}
D pin Setup/Hold with respect to CLK
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
D pin Setup/Hold with respect to CLK⁽¹⁾
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
D pin Setup/Hold with respect to CLK at DDR mode
(IOBDELAY = IBUF or NONE)
T_{ISDCK_DDR} / T_{ISCKD_DDR}
D pin Setup/Hold with respect to CLK at DDR mode
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
D pin Setup/Hold with respect to CLK at DDR mode⁽¹⁾
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
Sequential Delays
T_{ISCKO_Q}
Propagation Delays
CLKDIV to out at Q pin
T_{ISDO_DO_IOBDELAY_IFD}
T_{ISDO_DO_IOBDELAY_NONE}
T_{ISDO_DO_IOBDELAY_BOTH}
D input to DO output pin (IOBDELAY = IFD)
D input to DO output pin (IOBDELAY = NONE)
D input to DO output pin (IOBDELAY = BOTH,
IOBDELAY_TYPE = DEFAULT)
D input to DO output pin⁽¹⁾ (IOBDELAY = BOTH,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
T_{ISDO_DO_IOBDELAY_IBUF}
D input to DO output pin (IOBDELAY = IBUF,
IOBDELAY_TYPE = DEFAULT)
D input to DO output pin⁽¹⁾ (IOBDELAY = IBUF,
IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0)
Notes:
1. Recorded at 0 tap value. Refer to Timing Report for other values.
2. T_{ISCCK_CE2} and T_{ISCKC_CE2} are reported as T_{ISCCK_CE} / T_{ISCKC_CE} in TRCE report.
Speed Grade
-12
-11
-10
0.28
–0.20
0.48
–0.37
0.11
–0.04
0.16
0.11
0.01
0.36
–0.03
0.37
0.64
0.34
–0.16
0.57
–0.30
0.14
–0.03
0.19
0.13
0.01
0.43
–0.02
0.45
0.77
0.40
–0.13
0.69
–0.25
0.16
–0.02
0.23
0.16
0.01
0.51
–0.02
0.54
0.92
0.24
–0.11
6.64
–6.51
0.28
–0.11
7.63
–6.51
0.34
–0.11
8.84
–6.51
0.81
–0.68
0.24
–0.11
6.64
–6.51
0.87
–0.68
0.28
–0.11
7.63
–6.51
1.08
–0.68
0.34
–0.11
8.84
–6.51
0.81
–0.68
0.87
–0.68
1.08
–0.68
0.59
0.71
0.85
0.17
0.20
0.24
0.17
0.20
0.24
6.00
6.91
7.96
0.74
0.79
0.99
6.00
6.91
7.96
0.74
0.79
0.99
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
28