XC4VLX100-11FF1148C Datasheet, PDF (39/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 45: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode (Continued)
Speed Grade
Symbol
Description
-12
-11
-10 Units
CLKOUT_FREQ_FX_HF_MS_MIN
CLKOUT_FREQ_FX_HF_MS_MAX
CLKFX, CLKFX180
210
210
210 MHz
350
315
300 MHz
Input Clocks (High Frequency Mode)
CLKIN_FREQ_DLL_HF_MS_MIN⁽⁶⁾
CLKIN_FREQ_DLL_HF_MS_MAX
CLKIN (using DLL outputs only)^(1,3,4,5)
150
150
150 MHz
500
450
400 MHz
CLKIN_FREQ_FX_HF_MS_MIN
CLKIN_FREQ_FX_HF_MS_MAX⁽⁶⁾
CLKIN (using DFS outputs)^(2,3,4)
50
50
50
MHz
350
315
300 MHz
PSCLK_FREQ_HF_MS_MIN
PSCLK_FREQ_HF_MS_MAX
PSCLK
1
1
1
KHz
500
450
400 MHz
Notes:
1. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled.
4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55 to
55/45).
5. The DCM must be reset if the clock input clock stops for more than 100 ms.
6. These values also apply when using both DLL and DFS outputs.
Table 46: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode
Speed Grade
Symbol
Description
-12
-11
-10 Units
Outputs Clocks (Low Frequency Mode)
CLKOUT_FREQ_1X_LF_MR_MIN
CLKOUT_FREQ_1X_LF_MR_MAX
CLK0, CLK90, CLK180, CLK270
19
19
19
MHz
40
36
32
MHz
CLKOUT_FREQ_2X_LF_MR_MIN
CLKOUT_FREQ_2X_LF_MR_MAX
CLK2X, CLK2X180
38
38
38
MHz
80
72
64
MHz
CLKOUT_FREQ_DV_LF_MR_MIN
CLKOUT_FREQ_DV_LF_MR_MAX
CLKDV
1.2
1.2
1.2
MHz
26.7
24
21.3 MHz
CLKOUT_FREQ_FX_LF_MR_MIN
CLKOUT_FREQ_FX_LF_MR_MAX
CLKFX, CLKFX180
19
19
19
MHz
40
36
32
MHz
Input Clocks (Low Frequency Mode)
CLKIN_FREQ_DLL_LF_MR_MIN
CLKIN_FREQ_DLL_LF_MR_MAX
CLKIN (using DLL outputs)^(1,3,4,5,6)
19
19
19
MHz
40
36
32
MHz
CLKIN_FREQ_FX_LF_MR_MIN
CLKIN_FREQ_FX_LF_MR_MAX
CLKIN (using DFS outputs only)^(2,3,4)
1
1
1
MHz
35
32
28
MHz
PSCLK_FREQ_LF_MR_MIN
PSCLK_FREQ_LF_MR_MAX
PSCLK
1
1
262.50 236.30
1
210.00
KHz
MHz
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled.
4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55 to
55/45).
5. The DCM must be reset if the clock input clock stops for more than 100 ms.
6. These values also apply when using both DLL and DFS outputs.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
39