XC4VLX100-11FF1148C Datasheet, PDF (49/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
ChipSync™ Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-4 FPGA
source-synchronous transmitter and receiver data-valid windows.
Table 59: Duty Cycle Distortion and Clock-Tree Skew
Symbol
Description
Device
Speed Grade
-12
-11
-10
Units
T_{DCD_CLK}
T_CKSKEW
Global Clock Tree Duty Cycle Distortion⁽¹⁾
Global Clock Tree Skew⁽²⁾
All
150
150
150
ps
XC4VLX15
50
60
60
ps
XC4VLX25
90
100
110
ps
XC4VLX40
140
160
180
ps
XC4VLX60
140
160
180
ps
XC4VLX80
200
230
260
ps
XC4VLX100
270
310
350
ps
XC4VLX160
270
310
350
ps
XC4VLX200
N/A
310
350
ps
XC4VSX25
50
60
70
ps
XC4VSX35
90
100
120
ps
XC4VSX55
140
170
190
ps
XC4VFX12
50
60
70
ps
XC4VFX20
60
70
70
ps
XC4VFX40
90
110
120
ps
XC4VFX60
140
170
190
ps
XC4VFX100
200
230
260
ps
XC4VFX140
N/A
310
350
ps
T_{DCD_BUFIO}
I/O clock tree duty cycle distortion
I/O clock tree skew across one clock region
All
100
100
100
ps
All
50
50
50
ps
T_BUFIOSKEW
I/O clock tree skew across multiple clock regions
All
50
50
50
ps
T_{DCD_BUFR}
Regional clock tree duty cycle distortion
All
250
250
250
ps
T_{BUFIO_MAX_FREQ} I/O clock tree MAX frequency
All
710
710
645 MHz
T_{BUFR_MAX_FREQ}
Regional clock tree MAX frequency
All
300
250
250 MHz
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where
other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.
2. The T_CKSKEW value represents the worst-case vertical clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing
Analyzer tools to evaluate clock skew specific to your application.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
49