XC4VLX100-11FF1148C Datasheet, PDF (29/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Input Delay Switching Characteristics
Table 35: Input Delay Switching Characteristics
Speed Grade
Symbol
Description
-12
-11
-10
Units
IDELAYCTRL
T_{IDELAYCTRLCO_RDY}
Reset to Ready for IDELAYCTRL
(Maximum)
3.00
3.00
3.00
µs
F_{IDELAYCTRL_REF}
IDELAYCTRL_REF_PRECISION ⁽²⁾
REFCLK frequency
REFCLK precision
200
200
200
MHz
±10
±10
±10
MHz
T_{IDELAYCTRL_RPW}
IDELAY
Minimum Reset pulse width
50.0
50.0
50.0
ns
T_{IDELAYRESOLUTION}
T_{IDELAYTOTAL_ERR}
IDELAY Chain Delay Resolution
Cumulative delay at a given tap⁽³⁾
75
75
75
ps
[(tap −1) x 75 +34]
± 0.07[(tap −1) x 75 +34]
ps
T_{IDELAYPAT_JIT}
Pattern dependent period jitter in delay
chain for clock pattern
Pattern dependent period jitter in delay
chain for random data pattern (PRBS 23)
0
10 ± 2
0
10 ± 2
0
10 ± 2
Note (4)
Note (4)
F_MAX
C clock maximum frequency
300
250
250
MHz
Notes:
1. Refer to Xilinx Application Note XAPP707 for details on IDELAY timing characteristics.
2. See the “REFCLK - Reference Clock” section (specific to IDELAYCTRL) in the Virtex-4 FPGA User Guide: Chapter 7, SelectIO Logic Resources.
3. This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps.
4. Units in ps peak-to-peak per tap.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
29