XC4VLX100-11FF1148C Datasheet, PDF (43/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 51: Frequency Synthesis
Attribute
CLKFX_MULTIPLY
CLKFX_DIVIDE
Min
Max
2
32
1
32
Table 52: DCM Switching Characteristics
Symbol
Description
T_{DMCCK_PSEN} / T_{DMCKC_PSEN}
PSEN Setup/Hold
T_{DMCCK_PSINCDEC} / T_{DMCKC_PSINCDEC} PSINCDEC Setup/Hold
T_{DMCKO_PSDONE}
Clock to out of PSDONE
Speed Grade
-12
-11
-10
0.93 0.93 1.07
0.00 0.00 0.00
0.93 0.93 1.07
0.00 0.00 0.00
0.60 0.60 0.69
Units
ns
ns
ns
Table 53: PMCD Switching Characteristic
Symbol
Description
T_{PMCCCK_REL} / T_{PMCCKC_REL}
REL Setup/Hold for all outputs
T_{PMCCO_CLK{A1,B,C,D}}
T_{PMCCKO_CLK{A1,B,C,D}}
PMCD_CLK_SKEW
CLKIN_FREQ_PMCD_CLKA_MAX⁽¹⁾
RST assertion to clock output deassertion
Max clock propagation delay of PMCD for all outputs
Max phase between all outputs assuming all inputs
Max input/output frequency
CLKIN_PSCLK_PULSE_RANGE
Max duty cycle input tolerance (same as DCM)
PMCD_REL_HIGH_PULSE_MIN
Min pulse width for REL
PMCD_RST_HIGH_PULSE_MIN
Min pulse width for RST
Notes:
1. There is no minimum frequency for PMCD.
2. Refer to Table 47 parameter: CLKIN_PSCLK_PULSE_RANGE.
Speed Grade
-12
-11
-10
0.60 0.60 0.60
0.00 0.00 0.00
4.00 4.00 4.50
4.60 4.60 5.20
±150 ±150 ±150
500
450
400
Note (2)
1.11 1.11 1.25
1.11 1.11 1.25
Units
ns
ns
ns
ps
MHz
ns
ns
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
43