XC4VLX100-11FF1148C Datasheet, PDF (51/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 61: Sample Window
Symbol
Description
Device
Speed Grade
-12
-11
-10
Units
T_SAMP
T_{SAMP_BUFIO}
Sampling Error at Receiver Pins⁽¹⁾
Sampling Error at Receiver Pins using BUFIO⁽²⁾
All
450
500
550
ps
All
350
400
450
ps
Notes:
1. This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Table 62: ChipSync Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Description
Speed Grade
-12
-11
-10
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
T_PSCS / T_PHCS
Setup/Hold of I/O clock across multiple clock regions
–0.45
0.97
–0.45
1.08
–0.44
1.17
Pin-to-Pin Clock-to-Out Using BUFIO
T_ICKOFCS
Clock-to-Out of I/O clock across multiple clock regions
4.10
4.54
5.02
Units
ns
ns
Production Stepping
The Virtex-4 FPGA stepping identification system denotes
the capability improvement of production released devices.
By definition, devices from one stepping are functional
supersets of previous devices. Bitstreams compiled for a
device with an earlier stepping are guaranteed to operate
correctly in subsequent device steppings.
New device steppings can be shipped in place of earlier
device steppings. Existing production designs are guaran-
teed on new device steppings. To take advantage of the
capabilities of a newer device stepping, customers are able
to order a new stepping version and compile a new bit-
stream.
Production devices are marked with a stepping version, with
the exception of some step 1 devices. Designs should be
compiled with a CONFIG STEPPING parameter set to a
specific stepping version. This parameter is set in the UCF
file:
CONFIG STEPPING = “#”; (where # is the stepping
version)
The default stepping level used by the ISE software is
reported in the PAR report.
Table 63 shows the JTAG ID code by step.
Table 63: JTAG ID Code by Step
Device
Step 0
Step 1
Step 2
XC4VLX15
3
5
XC4VLX25
9
A
XC4VLX40
3
5
XC4VLX60
2 or 3
4 or 5
XC4VLX80
3
5
XC4VLX100
2 or 3
4 or 5
XC4VLX160
0 or 3
4 or 5
XC4VLX200
0 or 3
2 or 5
XC4VSX25
2
4
XC4VSX35
2
4
XC4VSX55
2
4
XC4VFX12
0 or 2
XC4VFX20
2
6
XC4VFX40
0
XC4VFX60
2
8
XC4VFX100
0
6
XC4VFX140
0
4
Notes:
1. Shaded cells represent devices not produced at that stepping.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
51