XC4VLX100-11FF1148C Datasheet, PDF (13/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device.
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotate to the
simulation net list. Unless otherwise noted, values apply to
all Virtex-4 devices.
PowerPC Switching Characteristics
Consult the PowerPC 405 Processor Block Reference Guide for further information.
Table 15: PowerPC 405 Processor Clocks Absolute AC Characteristics
Speed Grade
-12
-11
-10
Description
Min
Max
Min
Max
Min
Max Units
Characteristics when APU Not Used
CPMC405CLOCK frequency^(1,4)
CPMDCRCLK⁽³⁾
CPMFCMCLK⁽³⁾
JTAGC405TCK frequency⁽²⁾
PLBCLK⁽³⁾
BRAMDSOCMCLK⁽³⁾
BRAMISOCMCLK⁽³⁾
0
450
0
400
0
350
MHz
0
450
0
400
0
350
MHz
NA
NA
NA
NA
NA
NA
MHz
0
225
0
200
0
175
MHz
0
450
0
400
0
350
MHz
0
450
0
400
0
350
MHz
0
450
0
400
0
350
MHz
Characteristics when APU Used
CPMC405CLOCK frequency^(1,4)
CPMDCRCLK⁽³⁾
CPMFCMCLK⁽³⁾
JTAGC405TCK frequency⁽²⁾
PLBCLK⁽³⁾
BRAMDSOCMCLK⁽³⁾
BRAMISOCMCLK⁽³⁾
0
333
0
275
0
233
MHz
0
333
0
275
0
233
MHz
0
333
0
275
0
233
MHz
0
166.5
0
137.5
0
116.5
MHz
0
333
0
275
0
233
MHz
0
333
0
275
0
233
MHz
0
333
0
275
0
233
MHz
Notes:
1. Worst-case DCM output clock jitter is included in these specifications.
2. The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is system dependent, and will
be much less.
3. The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. Integer clock ratios are required for the CPMC405CLOCK and
BRAMDSOCMCLK, CPMC405CLOCK and BRAMISOCMCLK, CPMC405CLOCK and CPMDCRCLK, CPMC405CLOCK and CPMFCMCLK, and
CPMC405CLOCK and PLBCLK. The integer ratios can be different for each interface. However, the achievable maximum is system dependent.
4. Maximum operating frequency of CPMC405CLOCK is specified with the input pin TIEC405DISOPERANDFWD connected to a logic 1.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
13