XC4VLX100-11FF1148C Datasheet, PDF (34/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 41: FIFO Switching Characteristics
Speed Grade
Symbol
Description
-12
-11
-10
Units
Sequential Delays
T_{FCKO_DO}
T_{FCKO_FLAGS}
T_{FCKO_POINTERS}
Clock CLK to DO output⁽²⁾
Clock CLK to FIFO flags outputs⁽³⁾
Clock CLK to FIFO pointer outputs⁽⁴⁾
Setup and Hold Times Before Clock CLK
0.72
0.80
0.92
ns, Max
0.93
1.04
1.19
ns, Max
1.16
1.29
1.48
ns, Max
T_{FDCK_DI} / T_{FCKD_DI}
DI input⁽⁵⁾
0.18
0.20
0.23
0.26
0.28
0.33
ns, Min
T_{FCCK_EN} / T_{FCKC_EN}
Enable inputs⁽⁶⁾
0.66
0.73
0.84
0.26
0.28
0.33
ns, Min
Reset Delays
T_{FCO_FLAGS}
Maximum Frequency
Reset RST to FLAGS⁽⁷⁾
1.32
1.46
1.68
ns, Max
F_MAX
FIFO in all modes
500.00 450.45 400.00
MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2. T_{FCKO_DO} includes parity output (T_{FCKO_DOP}).
3. T_{FCKO_FLAGS} includes the following parameters: T_{FCKO_AEMPTY}, T_{FCKO_AFULL}, T_{FCKO_EMPTY}, T_{FCKO_FULL}, T_{FCKO_RDERR}, T_{FCKO_WRERR.}
4. T_{FCKO_POINTERS} includes both T_{FCKO_RDCOUNT} and T_{FCKO_WRCOUNT.}
5. T_{FDCK_DI} includes parity inputs (T_{FDCK_DIP}).
6. T_{FCCK_EN} includes both WRITE and READ enable.
7. T_{FCO_FLAGS} includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT and WRCOUNT.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
34