XC4VLX100-11FF1148C Datasheet, PDF (37/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 43: Configuration Switching Characteristics (Continued)
Speed Grade
Symbol
Description
-12
-11
-10
Units
Boundary-Scan Port Timing Specifications
T_TAPTCK
T_TCKTAP
T_TCKTDO
F_TCK
TMS and TDI Setup time before TCK
TMS and TDI Hold time after TCK
TCK falling edge to TDO output valid
Maximum configuration TCK clock
frequency
1.0
1.0
1.0
ns, Min
2.0
2.0
2.0
ns, Min
6.0
6.0
6.0
ns, Max
66
66
66
MHz, Max
F_TCKB
Maximum Boundary-Scan TCK clock
frequency
50
50
50
MHz, Max
Dynamic Reconfiguration Port (DRP) for DCM
CLKIN_FREQ_DLL_HF_MS_MAX
Maximum frequency for DCLK
500
450
400 MHz, Max
T_{DMCCK_DADDR}/T_{DMCKC_DADDR}
DADDR Setup/Hold time
0.54
0.00
0.63
0.00
0.72
0.00
ns, Max
T_{DMCCK_DI}/T_{DMCKC_DI}
DI Setup/Hold time
0.54
0.00
0.63
0.00
0.72
0.00
ns, Max
T_{DMCCK_DEN}/T_{DMCKC_DEN}
DEN Setup/Hold time
0.58
0.00
0.58
0.00
0.58
0.00
ns, Max
T_{DMCCK_DWE}/T_{DMCKC_DWE}
DWE Setup/Hold time
0.58
0.00
0.58
0.00
0.58
0.00
ns, Max
T_{DMCKO_DO}
CLK to out of DO⁽²⁾
0
0
0
ns, Max
T_{DMCKO_DRDY}
CLK to out of DRDY
0.68
0.80
0.92
ns, Max
Notes:
1. T_{BCCCK_CE} and T_{BCCKC_CE} must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters
do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only
needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks.
2. DO holds until the next DRP operation.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
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