XC4VLX100-11FF1148C Datasheet, PDF (42/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 50: Miscellaneous Timing Parameters
Speed Grade
Symbol
Description
-12
-11
-10 Units
Time Required to Achieve LOCK
T_LOCK_DLL_240
T_LOCK_DLL_120_240
T_LOCK_DLL_60_120
T_LOCK_DLL_50_60
T_LOCK_DLL_40_50
T_LOCK_DLL_30_40
T_LOCK_DLL_24_30
T_LOCK_DLL_30
T_LOCK_FX_MAX
DLL output – Frequency range > 240 MHz ⁽²⁾
20
20
20
µs
DLL output – Frequency range 120 - 240 MHz ^(1,2)
63
63
63
µs
DLL output – Frequency range 60 - 120 MHz ^(1,2)
225
225
225
µs
DLL output – Frequency range 50 - 60 MHz^(1,2)
325
325
325
µs
DLL output – Frequency range 40 - 50 MHz ^(1,2)
500
500
500
µs
DLL output – Frequency range 30 - 40 MHz ^(1,2)
900
900
900
µs
DLL output – Frequency range 24 - 30 MHz^(1,2)
1250 1250 1250 µs
DLL output – Frequency range < 30 MHz ⁽²⁾
1250 1250 1250 µs
DFS outputs⁽³⁾
10
10
10
ms
T_LOCK_DLL_FINE_SHIFT
Multiplication factor for DLL lock time with Fine Shift
2
2
2
Fine Phase Shifting
FINE_SHIFT_RANGE_MS
Absolute shifting range in maximum speed mode
7
7
7
ns
FINE_SHIFT_RANGE_MR
Absolute shifting range in maximum range mode
10
10
10
ns
Delay Lines
DCM_TAP_MS_MIN
Tap delay resolution (Min) in maximum speed mode
5
5
5
ps
DCM_TAP_MS_MAX
Tap delay resolution (Max) in maximum speed mode 40
40
40
ps
DCM_TAP_MR_MIN
Tap delay resolution (Min) in maximum range mode 10
10
10
ps
DCM_TAP_MR_MAX
Tap delay resolution (Max) in maximum range mode 60
60
60
ps
Input Signal Requirements
DCM_RESET⁽⁴⁾
Minimum duration that RST must be held asserted
200
200
200
ms
Maximum duration that RST can be held asserted⁽⁵⁾ 10
10
10 sec
DCM_INPUT_CLOCK_STOP
Maximum duration that CLKIN and CLKFB can be
stopped^(6,7)
100
100
100
ms
Notes:
1. For boundary frequencies, choose the higher delay.
2. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
3. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
4. CLKIN must be present and stable during the DCM_RESET.
5. This only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in Answer Record 21127 for support
of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement.
6. For production step 1 LX and SX devices, use the design solutions described in Answer Record 21127 for support of longer durations of stopped
clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small macro to support
longer durations of stopped clocks.
7. For all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
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