XC4VLX100-11FF1148C Datasheet, PDF (44/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
System-Synchronous Switching Characteristics
Virtex-4 FPGA Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 54. Values are expressed in nanoseconds unless otherwise noted.
Table 54: Global Clock Input to Output Delay for LVCMOS25 Standard, 12 mA, Fast Slew Rate, with DCM
Symbol
Description
Device
Speed Grade
-12
-11
-10
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM.
T_ICKOFDCM
Global Clock and OFF with DCM
XC4VLX15
2.43
2.81
3.25
ns
XC4VLX25
2.60
2.95
3.36
ns
XC4VLX40
2.54
2.91
3.32
ns
XC4VLX60
2.69
3.05
3.45
ns
XC4VLX80
2.88
3.27
3.72
ns
XC4VLX100 2.94
3.33
3.79
ns
XC4VLX160 2.94
3.35
3.82
ns
XC4VLX200
N/A
3.51
4.02
ns
XC4VSX25
2.65
2.99
3.39
ns
XC4VSX35
2.81
3.18
3.60
ns
XC4VSX55
2.83
3.20
3.62
ns
XC4VFX12
2.43
2.78
3.18
ns
XC4VFX20
2.54
2.88
3.26
ns
XC4VFX40
2.87
3.25
3.67
ns
XC4VFX60
2.92
3.31
3.77
ns
XC4VFX100 3.16
3.58
4.06
ns
XC4VFX140
N/A
3.79
4.30
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
44