XC4VLX100-11FF1148C Datasheet, PDF (23/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 30 shows the test setup parameters used for measuring input delay.
Table 30: Input Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)
I/O Standard
Attribute
LVTTL
V_L ^(1,2)
0
V_H ^(1,2)
3.0
V_MEAS
(1,4,5)
1.4
V_REF
(1,3,5)
–
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS33
0
3.3
1.65
–
LVCMOS, 2.5V
LVCMOS25
0
2.5
1.25
–
LVCMOS, 1.8V
LVCMOS18
0
1.8
0.9
–
LVCMOS, 1.5V
LVCMOS15
0
1.5
0.75
–
PCI (Peripheral Component Interface),
33 MHz, 3.3V
PCI33_3
Per PCI™ Specification
–
PCI, 66 MHz, 3.3V
PCI66_3
Per PCI Specification
–
PCI-X, 133 MHz, 3.3V
PCIX
Per PCI-X™ Specification
–
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic),
Class I & II
GTL
GTLP
HSTL_I, HSTL_II
V_REF – 0.2
V_REF – 0.2
V_REF – 0.5
V_REF + 0.2
V_REF + 0.2
V_REF + 0.5
V_REF
V_REF
V_REF
0.80
1.0
0.75
HSTL, Class III & IV
HSTL, Class I & II, 1.8V
HSTL, Class III & IV, 1.8V
HSTL_III, HSTL_IV
HSTL_I_18, HSTL_II_18
HSTL_III_18,
HSTL_IV_18
V_REF – 0.5
V_REF – 0.5
V_REF – 0.5
V_REF + 0.5
V_REF + 0.5
V_REF + 0.5
V_REF
V_REF
V_REF
0.90
0.90
1.08
SSTL (Stub Terminated Transceiver Logic),
Class I & II, 3.3V
SSTL3_I, SSTL3_II
V_REF – 1.00 V_REF + 1.00 V_REF
1.5
SSTL, Class I & II, 2.5V
SSTL, Class I & II, 1.8V
AGP-2X/AGP (Accelerated Graphics Port)
LVDS (Low-Voltage Differential Signaling), 2.5V
SSTL2_I, SSTL2_II
SSTL18_I, SSTL18_II
AGP
LVDS_25
V_REF – 0.75
V_REF – 0.5
V_REF –
(0.2 xV_CCO)
1.2 – 0.125
V_REF + 0.75
V_REF + 0.5
V_REF +
(0.2 xV_CCO)
1.2 + 0.125
V_REF
V_REF
V_REF
1.2
1.25
0.90
AGP
Spec
LVDSEXT (LVDS Extended Mode), 2.5V
LVDSEXT_25
1.2 – 0.125 1.2 + 0.125
1.2
ULVDS (Ultra LVDS), 2.5V
ULVDS_25
0.6 – 0.125 0.6 + 0.125
0.6
LDT (HyperTransport), 2.5V
LDT_25
0.6 – 0.125 0.6 + 0.125
0.6
Notes:
1. Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage.
Parameters for all other DCI standards are the same as for the corresponding non-DCI standards.
2. Input waveform switches between V_Land V_H.
3. Measurements are made at typical, minimum, and maximum V_REF values. Reported delays reflect worst case of these measurements. V_REF values
listed are typical.
4. Input voltage level from which measurement starts.
5. This is an input voltage reference that bears no relation to the V_REF / V_MEAS parameters found in IBIS models and/or noted in Figure 4.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
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