XC4VLX100-11FF1148C Datasheet, PDF (47/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 57: Global Clock Setup and Hold for LVCMOS25 Standard, with DCM in Source-Synchronous Mode
Speed Grade
Symbol
Description
Device
–12
–11
–10 Units
Example Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin,⁽¹⁾ Using DCM and Global Clock Buffer. For
situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values
shown in IOB Switching Characteristics^(1,2), page 19.
T_{PSDCM_0} /
T_{PHDCM_0}
No Delay Global Clock and IFF⁽²⁾ with DCM in
Source-Synchronous Mode
XC4VLX15
–0.33
0.73
–0.33
0.88
–0.33
1.03
ns
XC4VLX25
–0.29
0.86
–0.29
0.97
–0.29
1.09
ns
XC4VLX40
–0.37
0.90
–0.37
1.04
–0.37
1.19
ns
XC4VLX60
–0.32
1.02
–0.32
1.15
–0.32
1.29
ns
XC4VLX80
–0.38
1.18
–0.38
1.34
–0.38
1.50
ns
XC4VLX100
–0.31
1.24
–0.31
1.41
–0.31
1.57
ns
XC4VLX160
–0.31
1.50
–0.31
1.69
–0.31
1.89
ns
XC4VLX200
N/A
–0.31
1.97
–0.31
2.19
ns
XC4VSX25
–0.32
0.95
–0.32
1.07
–0.32
1.17
ns
XC4VSX35
–0.37
1.04
–0.37
1.17
–0.37
1.31
ns
XC4VSX55
–0.32
1.22
–0.32
1.36
–0.32
1.52
ns
XC4VFX12
–0.26
0.73
–0.26
0.86
–0.26
0.96
ns
XC4VFX20
–0.31
0.92
–0.31
1.03
–0.31
1.14
ns
XC4VFX40
–0.35
1.26
–0.35
1.41
–0.35
156
ns
XC4VFX60
–0.43
1.39
–0.43
1.56
–0.43
1.74
ns
XC4VFX100
–0.38
1.55
–0.38
1.75
–0.38
1.96
ns
XC4VFX140
N/A
–0.44
2.03
–0.44
2.25
ns
Notes:
1. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CLK0 DCM jitter. Package
skew is not included in these measurements.
2. IFF = Input Flip-Flop
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
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