XC4VLX100-11FF1148C Datasheet, PDF (15/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 19: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics
Speed Grade
Description
Symbol
-12
-11
-10
Setup and Hold Relative to Clock (BRAMDSOCMCLK)
Data-Side On-Chip Memory data bus inputs
Clock to Out
T_PPCDCK_DSOCMRDDB
T_PPCCKD_DSOCMRDDB
0.60
0.65
0.74
0.20
0.20
0.23
Data-Side On-Chip Memory control outputs
T_PPCCKO_BRAMBWR
Data-Side On-Chip Memory address bus outputs T_PPCCKO_BRAMABUS
Data-Side On-Chip Memory data bus outputs
T_PPCCKO_IBRAMWRDBUS01
2.07
2.30
2.65
2.07
2.30
2.65
1.61
1.79
2.06
Units
ns, Min
ns, Max
ns, Max
ns, Max
Table 20: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics
Speed Grade
Description
Symbol
-12
-11
-10
Setup and Hold Relative to Clock (BRAMISOCMCLK)
Instruction-Side On-Chip Memory data bus inputs
Clock to Out
T_PPCDCK_ISOCMRDDB
T_PPCCKD_ISOCMRDDB
0.74
0.82
0.94
0.20
0.20
0.23
Instruction-Side On-Chip Memory control outputs
T_PPCCKO_IBRAMEN
3.04
3.37
3.88
Instruction-Side On-Chip Memory address bus outputs T_PPCCKO_IBRAMRDABUS
1.67
1.85
2.13
Instruction-Side On-Chip Memory data bus outputs T_PPCCKO_IBRAMWRDBUS 1.67
1.86
2.14
Units
ns, Min
ns, Max
ns, Max
ns, Max
Table 21: Processor Block DCR Bus Switching Characteristics
Description
Symbol
Setup and Hold Relative to Clock (CPMDCRCLOCK)
Device Control Register Bus control inputs
Device Control Register Bus data inputs
Clock to Out
T_PPCDCK_EXDCRACK
T_PPCCKD_EXDCRACK
T_PPCDCK_EXDCRDBUSI
T_PPCCKD_EXDCRDBUSI
Device Control Register Bus control outputs
Device Control Register Bus address bus outputs
Device Control Register Bus data bus outputs
T_PPCCKO_EXDCRRD
T_PPCCKO_EXDCRABUS
T_PPCCKO_EXDCRDBUSO
Speed Grade
-12
-11
-10
Units
0.12
0.15
0.13
0.17
0.15
0.19
ns, Min
0.57
0.16
0.57
0.16
1.02
0.27
ns, Min
1.20
1.35
1.54 ns, Max
1.28
1.45
1.66 ns, Max
1.31
1.45
1.67 ns, Max
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
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