XC4VLX100-11FF1148C Datasheet, PDF (25/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 31: Output Delay Measurement Methodology (Continued)
Description
I/O Standard
Attribute
HSTL, Class IV, 1.8V
HSTL_IV_18
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL18_I
SSTL, Class II, 1.8V
SSTL18_II
SSTL, Class I, 2.5V
SSTL2_I
SSTL, Class II, 2.5V
SSTL2_II
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS_25
LVDSEXT (LVDS Extended Mode), 2.5V
LVDSEXT_25
BLVDS (Bus LVDS), 2.5V
BLVDS_25
LDT (HyperTransport), 2.5V
LDT_25
LVPECL (Low-Voltage Positive Emitter-Coupled Logic),
2.5V
LVPECL_25
LVDCI/HSLVDCI
(Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI_33, HSLVDCI_33
LVDCI/HSLVDCI, 2.5V
LVDCI_25, HSLVDCI_25
LVDCI/HSLVDCI, 1.8V
LVDCI_18, HSLVDCI_18
LVDCI/HSLVDCI, 1.5V
LVDCI_15, HSLVDCI_15
HSTL (High-Speed Transceiver Logic), Class I & II, with
DCI
HSTL_I_DCI, HSTL_II_DCI
HSTL, Class III & IV, with DCI
HSTL_III_DCI, HSTL_IV_DCI
HSTL, Class I & II, 1.8V, with DCI
HSTL_I_DCI_18,
HSTL_II_DCI_18
HSTL, Class III & IV, 1.8V, with DCI
HSTL_III_DCI_18,
HSTL_IV_DCI_18
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI
SSTL, Class I & II, 2.5V, with DCI
SSTL2_I_DCI, SSTL2_II_DCI
GTL (Gunning Transceiver Logic) with DCI
GTL_DCI
GTL Plus with DCI
GTLP_DCI
Notes:
1. C_REF is the capacitance of the probe, nominally 0 pF.
2. Per PCI specifications.
3. Per PCI-X specifications.
R_REF
( Ω)
25
50
25
50
25
50
50
1M
50
C_REF⁽¹⁾
( pF )
0
0
0
0
0
0
0
0
0
V_MEAS
(V)
1.1
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
1.2
V_REF
V_REF
(V)
1.8
0.9
0.9
1.25
1.25
1.2
1.2
0
0.6
1M
0
0.90
0
1M
0
1.65
0
1M
0
1M
0
1M
0
1.25
0
0.9
0
0.75
0
50
0
V_REF 0.75
50
0
0.9
1.5
50
0
V_REF
0.9
50
0
1.1
1.8
50
0
V_REF
0.9
50
0
V_REF 1.25
50
0
0.8
1.2
50
0
1.0
1.5
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
25