XC4VLX100-11FF1148C Datasheet, PDF (30/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 36: OSERDES Switching Characteristics
Symbol
Setup/Hold
T_{OSDCK_D} / T_{OSCKD_D}
Description
D input Setup/Hold with respect to CLKDIV
T_{OSDCK_T} / T_{OSCKD_T(1)}
T input Setup/Hold with respect to CLK
T_{OSDCK_T2} / T_{OSCKD_T2(1)}
T input Setup/Hold with respect to CLKDIV
T_{OSCCK_OCE} / T_{OSCKC_OCE} OCE input Setup/Hold with respect to CLK
T_{OSCCK_S}
SR (Reset) input Setup with respect to CLKDIV
T_{OSCCK_TCE} / T_{OSCKC_TCE}
TCE input Setup/Hold with respect to CLK
Sequential Delays
T_{OSCKO_OQ}
T_{OSCKO_TQ}
Combinatorial
Clock to out from CLK to OQ
Clock to out from CLK to TQ
T_{OSDO_TTQ}
T input to TQ Out
T_{OSCO_OQ}
Asynchronous Reset to OQ
T_{OSCO_TQ}
Asynchronous Reset to TQ
Notes:
1. T_{OSDCK_T2} and T_{OSCKD_T2} are reported as T_{OSDCK_T} / T_{OSCKD_T} in TRCE report.
Speed Grade
-12
-11
-10
Units
0.35
–0.05
0.42
–0.04
0.50
–0.03
ns
0.43
–0.16
0.52
–0.16
0.62
–0.16
ns
0.35
–0.05
0.42
–0.04
0.50
–0.03
ns
0.45
0.01
0.53
0.02
0.64
0.03
ns
0.67
0.80
0.96
ns
0.45
0.01
0.53
0.02
0.64
0.03
ns
0.41
0.49
0.59
ns
0.41
0.49
0.59
ns
0.56
0.65
0.76
ns
1.14
1.37
1.64
ns
1.14
1.37
1.64
ns
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
30