XC4VLX100-11FF1148C Datasheet, PDF (53/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Revision History
The following table shows the revision history for this document.
Date
08/02/04
09/09/04
01/18/05
02/01/05
02/24/05
05/19/05
06/17/05
06/27/05
08/06/05
08/29/05
09/28/05
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
Revisions
Initial Xilinx release. Printed Handbook version.
Edits in Tables 12, 13, 18, 19, 20, 22, 26, 28, 37, and 38. Removed Table 39.
Added parameters to Tables 4 and 5. Removed System Monitor and ADC parameters.
Changed parameters in Tables 1, 2, 3, 7, and 11. Added Interface Performance
Characteristics section. Added Switching Characteristics section and Table 14. Added
parameters to the following tables: 4–6, 14, 16–30, 32–40, and 46.
Changed the notes in Table 2. Added Set/Reset parameters to Table 32 and Table 33.
Changed description in Table 35. Changed Set/Reset in Table 37. Changed PSCLK units in
Table 45. Added parameters to Table 46. Changed DCM_TAP_MS_MIN in Table 50.
Added RocketIO and PowerPC parameters to Table 1, Table 2, and Table 3. Removed
conditions from V_IDIFF and V_ICM in Table 9. Revised Table 13. Added RocketIO DC Input
and Output Levels section. Added PowerPC Switching Characteristics section. Added
RocketIO Switching Characteristics section. Removed Table 31 from version 1.4.
Revised Table 35. Along with changes to Table 43 and Table 50, there are three new
requirements to ensure maximum operating frequencies for the DCM. Added parameters to
Table 54, Table 55, Table 56, Table 58, Table 59, Table 60, Table 61, Table 62.
Revised V_IN and V_TS in Table 1 and Note 4. Revised typical P_CPU specification in Table 3.
Revised symbols and values in the Processor tables: Table 16 through Table 22. Revised
T_DCREF in Table 24. Corrected the CLKOUT_FREQ_FX_HF_MS_MIN in Table 45, the
CLKOUT_FREQ_FX_LF_MR_MIN in Table 46, and the “Input Clock Period Jitter” in
Table 47. Corrected units in Table 59.
Changed V_IL and V_IH for LVCMOS15 in Table 7. Revised Table 14. Replaced value for V_EYE
in Table 25. Added Note 4 to Table 50. Added Table 57: Global Clock Setup and Hold for
LVCMOS25 Standard, with DCM in Source-Synchronous Mode. Added value for
XC4VLX160-FF1513 in Table 60. Added values for -12 speed specifications to most of the
tables. Revised the -10 and -11 speeds in most of the switching characteristics tables.
Updated to speed specification v1.56. Added V_{CC_CONFIG} note to Table 2. Clarified design
information in Table 13. Corrected T_PROGRAM in Table 43. Added DRP configuration timing
for DCMs to Table 43. Added global clock tree maximum frequency to Table 44. Corrected
CLKOUT_FREQ_FX_LF_MS_MIN in Table 45. Added footnotes 3 and 4 to Table 45 and
Table 46. Added more data to the T_CKSKEW in Table 59.
Corrected V_OCM in Table 8. Revised Table 11. Added RocketIO MGT Clock DC Input
Levels to Table 12. Revised SFI-4.1 performance values in Table 13. Added software tools
requirements ISE7.1i SP4, to description above Table 14. Added -11X speed grade to
Table 14 and Table 23. Edited Table 15 and Table 16. Edited Table 24. Added note 2 to
Table 25, and moved RXOOB_VDPP to Table 12. Added conditions to T_DJ and T_RJ in
Table 26. Moved TXOOB_VDPP to Table 12. Added RSDS to Table 27. Added note 4 to
Table 49. Added Production Stepping section.
Table 2: Removed Note 1. Recommended maximum voltage drop for V_CCAUX is 10 mV/ms.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
53