XC4VLX100-11FF1148C Datasheet, PDF (16/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 22: Processor Block APU Interface Switching Characteristics
Description
Symbol
Setup and Hold Relative to Clock (CPMDFCMCLOCK)
APU bus control inputs
APU bus data inputs
Clock to Out
T_PPCDCK_DCDCREN
T_PPCCKD_DCDCREN
T_PPCDCK_RESULT
T_PPCCKD_RESULT
APU bus control outputs
APU bus data outputs
T_PPCCKO_APUFCMDEC
T_PPCCKO_RADATA
Speed Grade
-12
-11
-10
0.33
0.36
0.42
0.20
0.20
0.23
0.61
0.67
0.78
0.20
0.20
0.23
1.53
1.75
2.00
1.53
1.75
2.00
RocketIO Switching Characteristics
Consult the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide for further information.
Table 23: Maximum RocketIO Transceiver Performance
RocketIO Transceiver
Description
Speed Grade
-12
-11
6.5
6.5
-10
3.125
Units
ns, Min
ns, Min
ns, Max
ns, Max
Units
Gb/s
Table 24: RocketIO Reference Clock Switching Characteristics
Description
Symbol
Conditions
Min Typ Max Units
-10 Speed Grade
Reference Clock frequency range⁽¹⁾
F_GCLK CLK
106
400
MHz
-11/-12 Speed Grades
106
644
MHz
GREFCLK Reference Clock frequency range⁽¹⁾
Reference Clock frequency tolerance
Reference Clock rise time
Reference Clock fall time
Reference Clock duty cycle
Reference Clock total jitter, peak-peak⁽²⁾
Clock recovery frequency acquisition time
Spread Spectrum Clocking⁽³⁾
F_GREFCLK
F_GTOL
T_RCLK
T_FCLK
T_DCREF
T_GJTT
T_LOCK
CLK
CLK
20% – 80%
20% – 80%
CLK
CLK
Initial lock of the PLL from
startup (programmable)
0% to –0.5%
106
–350
45
All Speed Grades
320
MHz
+350 ppm
400
ps
400
ps
55
%
40
ps
1
ms
30
33
kHz
Notes:
1. MGTCLK input can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to 1 Gb/s.
2. Measured at the package pin. For serial rates equal to or above 1 Gb/s, MGTCLK must be used. UI = Unit Interval.
3. Tested with synchronous reference clock.
T_RCLK
80%
20%
T_FCLK
DS302_04_031708
Figure 3: Reference Clock Timing Parameters
DS302 (v3.7) September 9, 2009
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Product Specification
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