XC4VLX100-11FF1148C Datasheet, PDF (55/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Date
09/07/06
10/06/06
12/11/06
Version
1.16
1.17
2.0
Revisions
Added 2.5V rows to V_IN and V_TS (Table 1, page 1). Updated value DV_IN from 200 mV to
110 mV in Table 12, page 11. Updated speed grade specifications for XCV4FX devices in
Table 14. Updated jitter tolerance and V_EYE in Table 25, page 17. Corrected equation for
T_{IDELAYTOTAL_ERR} in Table 35, page 29.
• SPEED SPECIFICATION version for this data sheet release: v1.62.
• Table 1: Removed former note 3 on V_IN.
• Table 14: Moved XC4VFX12-11, XC4VFX20-11, XC4VFX60-11, and XC4VFX100-11
devices to Production status.
• Table 15: Expanded to break out processor clock specifications into Characteristics
when APU Not Used and Characteristics when APU Used. Removed specs for
CPMFCMCLK, not available.
• Table 25, Table 26: Updated RX and TX jitter data and notes.
• Table 39: Modified T_REGXB, T_REGYB, and T_CKSH timing parameters to comply with
v1.62 speed specification.
• SPEED SPECIFICATION version for this data sheet release: v1.62.
• Table 1: Modified Note (3) referring to 3.3V I/O design guidelines. Added I_IN
parameters.
• Table 2: Corrected recommended V_TRX range to 0.25V – 2.5V. Added I_IN parameters.
• Table 7: Added LVDCI attributes with LVCMOS.
• Table 13: Added Note (1) for SDR LVDS Interface requiring AC coupling above
622 MHz. Added DDR2 SDRAM (High-Performance SERDES Design) with reference
to XAPP721. Updated all specification values.
• Pin-to-Pin Performance and Register-to-Register Performance tables (formerly Table
13 and Table 14) deleted.
• Table 14: XC4VFX12 changed to Production status.
• Table 15: Added APU-used max characteristics for -12 devices.
• Table 24: Added values for Spread-Spectrum Clocking and footnote.
• Table 26: Changed symbol for jitter parameters from T_J, R_J, and D_J to TJ, RJ, and DJ
respectively.
• Table 32: Added Note (1) to refer to Timing Report for non-zero tap values. Made DLY
setup/hold parameters relative to C, not CLKDIV.
• Table 34: Amended Note (1) to refer to Timing Report for non-zero tap values.
• Table 35: Added Note (1) to refer to XAPP707 for details on IDELAY timing
characteristics. Changed T_{IDELAYRESOLUTION} from 74 ps to 75 ps to match Timing
Analyzer. Modified formula for T_{IDELAYTOTAL_ERR} to use 75 ps resolution.
• Table 40: Added CLK-to-DOUT parameters for “with ECC” case. Added CLK-to-CLK
parameter.
• Table 43, Table 44, Table 59: Added configuration parameter values for -12 speed
grade.
• Table 45: Added F_MAX for -12 speed grade.
• Table 45, Table 46, Table 47: Added Note (6) stating that CLKIN values for DLL only
also apply to DLL and DFS together.
• Table 46, Table 47: Replicated Note (5) from Table 45 and applied to all CLKIN with
DLL parameters.
• Table 47, Table 50: Added notes to clarify boundary-frequency cases.
• Table 48: Modified Note (1) to point to the architecture wizard for CLKFX output jitter.
Added Note (2) to indicate that PMCD outputs introduce no jitter.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
55