XC4VLX100-11FF1148C Datasheet, PDF (41/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Output Clock Jitter
Table 48: Output Clock Jitter
Description
Symbol
Constraints
Clock Synthesis Period Jitter
CLK0
CLKOUT_PER_JITT_0
CLK90
CLKOUT_PER_JITT_90
CLK180
CLKOUT_PER_JITT_180
CLK270
CLKOUT_PER_JITT_270
CLK2X, CLK2X180
CLKOUT_PER_JITT_2X
CLKDV (integer division)
CLKOUT_PER_JITT_DV1
CLKDV (non-integer division)
CLKOUT_PER_JITT_DV2
CLKFX, CLKFX180
CLKOUT_PER_JITT_FX
Notes:
1. PMCD outputs are not included in this table because they do not introduce jitter.
2. Values for this parameter are available from the architecture wizard.
Speed Grade
-12
-11
-10
Units
±100 ±100 ±100
ps
±150 ±150 ±150
ps
±150 ±150 ±150
ps
±150 ±150 ±150
ps
±200 ±200 ±200
ps
±150 ±150 ±150
ps
±300 ±300 ±300
ps
Note (2) Note (2) Note (2) ps
Output Clock Phase Alignment
Table 49: Output Clock Phase Alignment
Speed Grade
Description
Symbol
Constraints
-12
-11
-10 Units
Phase Offset Between CLKIN and CLKFB
CLKIN / CLKFB
CLKIN_CLKFB_PHASE
±120 ±120 ±120
ps
Phase Offset Between Any DCM Outputs
All CLK outputs
CLKOUT_PHASE
±140 ±140 ±140
ps
Duty Cycle Precision
DLL outputs⁽¹⁾
DFS outputs⁽²⁾
CLKOUT_DUTY_CYCLE_DLL^(3,4)
CLKOUT_DUTY_CYCLE_FX⁽⁴⁾
±150 ±150 ±150
ps
±200 ±200 ±200
ps
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION=TRUE.
4. The measured value includes the duty cycle distortion of the global clock tree.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
41