XC4VLX100-11FF1148C Datasheet, PDF (35/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
XtremeDSP™ Switching Characteristics
Table 42: XtremeDSP Switching Characteristics
Symbol
Setup and Hold of CE Pins
T_{DSPCCK_CE} / T_{DSPCKC_CE}
Description
Setup/Hold of all CE inputs of the DSP48 slice
T_{DSPCCK_RST} / T_{DSPCKC_RST} Setup/Hold of all RST inputs of the DSP48 slice
Setup and Hold Times of Data
T_{DSPDCK_{AA, BB, CC}} /
T_{DSPCKD_{AA, BB, CC}}
T_{DSPDCK_{AM, BM}} /
T_{DSPCKD_{AM, BM}}
Sequential Delays
T_{DSPCKO_PP}
T_{DSPCKO_PM}
Combinatorial
T_{DSPDO_{AP, BP}L}
Maximum Frequency
F_MAX
Setup/Hold of {A, B, C} input to {A, B, C} register
Setup/Hold of {A, B} input to M register
Clock to out from P register to P output
Clock to out from M register to P output
{A, B} input to P output
(LEGACY_MODE = MULT18X18)
From {A, B} register to P register
(LEGACY_MODE = MULT18X18)
Fully Pipelined
Speed Grade
-12
-11
-10
0.39
0.43
0.49
0.09
0.10
0.12
0.32
0.36
0.40
0.09
0.10
0.12
0.25
0.28
0.32
0.23
0.26
0.29
1.82
2.03
2.28
0.00
0.00
0.00
0.64
0.71
0.79
2.38
2.65
2.98
Units
ns
ns
ns
ns
ns
ns
3.53
3.92
4.41
ns
317.46 285.71 253.94
500.00 450.05 400.00
MHz
MHz
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
35