XC4VLX100-11FF1148C Datasheet, PDF (54/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Date
02/03/06
03/22/06
06/01/06
06/23/06
08/23/06
Version
1.11
1.12
1.13
1.14.1
1.15
Revisions
Revised the speed specification requirements in Switching Characteristics, page 12, with
parameter changes in Table 54 and Table 56. Added Note 7 to Table 2. Added to the I_RPU
and I_RPD specifications in Table 3. Changed LVCMOS18 to meet the JEDEC specification in
Table 7. Inserted notes into Table 8, Table 9, and Table 10. Corrected note 1 in Table 11. In
Table 12, revised Common Mode Input Voltage Range (V_ICM) typical from 800 mV to
600 mV and added a new Note 1. Also in Table 12, changed Common Mode Voltage
specification from 95mV to 950mV. Changed performance numbers in Table 23. Removed
the typical specification for T_DJ from Table 26. Added note 2 to Table 27. In Table 35, added
maximum to T_{IDELAYCTRLCO_RDY}, and a new parameter T_{IDELAYPAT_JIT}. Revised Note 1 in
Table 43. Added note 5 to Table 45. Revised notes 3 and 5 in Table 50. Changed the
CLKIN_FREQ_PMCD_CLKA_MAX -12 specification in Table 53. Changed the
T_{BUFIO_MAX_FREQ} specification in Table 59. Changed the information in the Production
Stepping and Current Virtex-4 Production Devices sections.
Modified second paragraph in Power-On Power Supply Requirements. Added/Changed
numbers for I_CCINTMIN, I_CCAUXMIN, and I_CCOMIN, and added Note 2 (Table 5). Changed the
typ value of the DC Parameter, Common Mode Input Voltage Range from 600 MV to
800 MV in Table 12. Added three DC parameters to Table 12, Input Common-Mode Voltage
(V_ICMC), Peak-to-Peak Differential Input Voltage (V_IDIFF), and Differential Input Resistance
(R_IN). Changed the SPI4.2 entry for -11 from 900 Mb/s to 1 Gb/s in Table 13. Added Note 3
to Table 15. Reduced the maximum frequency from 322 MHz to 250 MHz (in Table 25 and
Table 26). Added Note 5 to Table 40.
Changed V_IN and V_TS values and added notes to Table 1, page 1. Removed -11X speed
grade from Table 14. Updated to speed specification v1.60. Removed -11X speed grade,
changed the -12 and -11 speed grade to 6.5 Gb/s, and deleted Note 1 in Table 23, page 16.
Deleted first condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Reference
Clock total jitter, peak-peak (T_GJTT) in Table 24, page 16. Changed the max value for Serial
data rate F_GTX to 6.5 Gb/s. Deleted first condition and changed second condition to
2.5 Gb/s to 6.5 Gb/s for Serial data output deterministic jitter (T_DJ) and deleted first
condition and changed second condition to 2.5 Gb/s to 6.5 Gb/s for Serial data output
random jitter (T_RJ), both in Table 26, page 18.
Virtex-4 FPGA Electrical Characteristics, page 1: removed paragraph on that introduced
the -11x for XC4VFX devices. Table 3, page 3: added new values for I_CCAUXRX, I_CCAUXTX,
I_CCCAUXMGT, I_TTX, I_TRX, and new notes 2 and 3. Table 4, page 4: added new symbols and
for values I_CCAUXRX, I_CCAUXTX, I_TTX , I_TRX,I_AUMGT and new notes 4 and 5. Table 12,
page 11: changed DC parameters and values and added note. Table 14: changed speed
designations for the XC4VFX devices. Table 24, page 16 and Table 25, page 17, for most
characteristics: changed conditions, speed grade (typ and max) values, and units. Table 26,
page 18, for most characteristics: changed conditions, speed grade (typ and max) values,
and units. Updated notes. Table 43, page 36: removed the Tcnfig symbol, values, and note
1. Note 2 is now Note 1, and the reference has also been changed. Table 50, page 42:
removed Input Signal Requirements. Table 54, page 44, Table 55, page 45, Table 56,
page 46, Table 57, page 47, and Table 58, page 48: corrected large speed numbers to N/A.
Table 24, page 16: changed value for Reference Clock Rise/Fall Time (T_RCLK; T_FCLK) from
65 ps Typ to 400 ps Max. Table 35, page 29: changed the speeds specification for the -12,
-11, and -10 Speed Grades for T_{IDELAYRESOLUTION}, deleted row for
T_{IDELAYRESOLUTION_ERR} and added row for T_{IDELAYTOTAL_ERR}. Table 39, page 32: changed
the speeds specification for -12 Speed Grades, Sequential Delay characteristics: T_REG,
T_REGXB, T_REGYB, T_CKSH, and T_REGF5. Table 65, page 52: added stepping information for
Virtex-4 FX devices.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
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