XC4VLX100-11FF1148C Datasheet, PDF (57/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Date
09/28/07
12/11/07
04/10/08
06/06/08
11/26/08
06/16/09
08/13/09
09/09/09
Version
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Revisions
• SPEED SPECIFICATION version for this data sheet release: v1.67.
• Promoted data sheet to Production status.
• Table 14: Moved XC4VFX140, all speed grades, from Advance to Production status.
• Table 59: Added/updated all Global Clock Tree Skew values. Qualified Note (2) by
adding “vertical”.
• Table 60: Added Package Skew values for XC4VFX40, XC4VFX100, and XC4VFX140.
• Table 63: Added JTAG ID code for XC4VFX140.
• SPEED SPECIFICATION version for this data sheet release: v1.68.
• Added new copyright notice and legal disclaimer section.
• Table 13: Removed table note references to XAPP700, XAPP704, and XAPP705
(obsolete). Renumbered table notes.
• Table 15: Added new Note 1, renumbered subsequent table notes.
• Table 30: Removed table rows for LVPECL_33, LVDS_33, and LVDSEXT_33.
• Table 30, Table 31: Corrected “electron-coupled” to “emitter-coupled”.
• Table 31: For LVDS Extended Mode 2.5V, corrected I/O Standard Attribute to
LVDSEXT_25.
• Table 37: Added Note 4 specifying F_TOG for -11 FX devices as 1181 MHz.
• Table 43: Added parameter F_{MAX_READBACK}.
• Table 58: Corrected T_PSFD for XC4VFX100 devices to 1.99 ns.
• Section Production Stepping, page 51: Advised that current stepping level is reported
by the ISE tool in the PAR report.
• SPEED SPECIFICATION version for this data sheet release: v1.68.
• Table 28, page 22: Re-inserted table.
• Table 43, page 36: Updated Symbol names for the DRP entries.
• Table 63, page 51: Revised code for XC4VFX40 package to 0.
• SPEED SPECIFICATION version for this data sheet release: v1.68.
• Table 3, page 3: In Note (2), clarified differences between settings for typical and
maximum I_CC numbers.
• Table 24, page 16: Revised F_GCLK to show different maximum frequencies depending
on the speed grade. Removed T_PHASE.
• Table 35, page 29: Reorganized according to IDELAYCTRL and IDELAY.
• Table 35, page 29: Added F_MAX.
• Table 40, page 33: Changed T_{RCKO_DOA} to a Max parameter.
• Table 3, page 3: Updated Note 1.
• Table 45, page 38: Added Note 6 reference to and updated descriptions of
CLKIN_FREQ_DLL_HF_MS_MIN and CLKIN_FREQ_FX_HF_MS_MAX.
• Table 7, page 8: Added “LVCMOS” to Notes 3 and 4.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
57