XC4VLX100-11FF1148C Datasheet, PDF (24/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4 inches
of FR4 microstrip trace. Standard termination was used for
all testing. The propagation delay of the 4 inch trace is char-
acterized separately and subtracted from the final measure-
ment, and is therefore not included in the generalized test
setup shown in Figure 4.
V_REF
FPGA Output
R_REF
V_MEAS
(voltage level when taking
delay measurement)
C_REF
(probe capacitance)
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. Parame-
ters V_REF, R_REF, C_REF, and V_MEAS fully describe the test
conditions for each I/O standard. The most accurate predic-
tion of propagation delay in any given application can be
obtained through IBIS simulation, using the following
method:
1. Simulate the output driver of choice into the generalized
test setup, using values from Table 31.
2. Record the time to V_MEAS.
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4. Record the time to V_MEAS.
5. Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual worst-case
propagation delay (clock-to-input) of the PCB trace.
DS302_05_031708
Figure 4: Generalized Test Setup
Table 31: Output Delay Measurement Methodology
Description
I/O Standard
Attribute
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVTTL (all)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS33
LVCMOS, 2.5V
LVCMOS25
LVCMOS, 1.8V
LVCMOS18
LVCMOS, 1.5V
LVCMOS15
LVCMOS, 1.2V
LVCMOS12
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI33_3 (rising edge)
PCI33_3 (falling edge)
PCI, 66 MHz, 3.3V
PCI66_3 (rising edge)
PCI66_3 (falling edge)
PCI-X, 133 MHz, 3.3V
PCIX (rising edge)
PCIX (falling edge
GTL (Gunning Transceiver Logic)
GTL
GTL Plus
GTLP
HSTL (High-Speed Transceiver Logic), Class I
HSTL_I
HSTL, Class II
HSTL_II
HSTL, Class III
HSTL_III
HSTL, Class IV
HSTL_IV
HSTL, Class I, 1.8V
HSTL_I_18
HSTL, Class II, 1.8V
HSTL_II_18
HSTL, Class III, 1.8V
HSTL_III_18
R_REF
( Ω)
1M
1M
1M
1M
1M
1M
25
25
25
25
25
25
25
25
50
25
50
25
50
25
50
C_REF⁽¹⁾
( pF )
0
0
0
0
0
0
10 ⁽²⁾
10 ⁽²⁾
10 ⁽²⁾
10 ⁽²⁾
10 ⁽³⁾
10 ⁽³⁾
0
0
0
0
0
0
0
0
0
V_MEAS
(V)
1.4
1.65
1.25
0.9
0.75
0.75
0.94
2.03
0.94
2.03
0.94
2.03
0.8
1.0
V_REF
V_REF
0.9
0.9
V_REF
V_REF
1.1
V_REF
(V)
0
0
0
0
0
0
0
3.3
0
3.3
3.3
1.2
1.5
0.75
0.75
1.5
1.5
0.9
0.9
1.8
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
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