XC4VLX100-11FF1148C Datasheet, PDF (31/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
CLB Switching Characteristics
Table 37: CLB Switching Characteristics
Speed Grade
-12
-11 -10
Symbol
Description
XC4VFX⁽²⁾ XC4VLX/SX ALL DEVICES
Units
Combinatorial Delays
T_ILO
4-input function: F/G inputs to X/Y outputs
T_IF5
5-input function: F/G inputs to F5 output
T_IF5X
5-input function: F/G inputs to X output
T_IF6Y
FXINA or FXINB inputs to YMUX output
T_INAFX
FXINA input to FX output via MUXFX
T_INBFX
FXINB input to FX output via MUXFX
T_BXX
BX input to XMUX output
T_BYY
BY input to YMUX output
T_BXCY
BX input to C_OUT output – Getting into carry chain⁽³⁾
T_BYCY
T_BYP
T_OPCYF
T_OPCYG
BY input to C_OUT output – Getting into carry chain⁽³⁾
C_IN input to C_OUT output – Carry chain delay⁽³⁾
F input to C_OUT output – Getting out from carry chain⁽³⁾
G input to C_OUT output – Getting out from carry chain⁽³⁾
Sequential Delays
0.15
0.36
0.44
0.30
0.21
0.21
0.59
0.43
0.60
0.49
0.07
0.45
0.44
0.15
0.17 0.20 ns, Max
0.35
0.40 0.46 ns, Max
0.43
0.49 0.57 ns, Max
0.30
0.34 0.39 ns, Max
0.21
0.23 0.27 ns, Max
0.20
0.23 0.26 ns, Max
0.58
0.65 0.76 ns, Max
0.43
0.48 0.56 ns, Max
0.59
0.66 0.78 ns, Max
0.48
0.54 0.63 ns, Max
0.07
0.08 0.09 ns, Max
0.44
0.50 0.58 ns, Max
0.43
0.48 0.57 ns, Max
T_CKO
FF Clock CLK to XQ/YQ outputs
T_CKLO
Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T_DICK / T_CKDI
BX/BY inputs
T_CECK / T_{CKCE CE input}
T_FXCK / T_{CKFX FXINA/FXINB inputs}
T_SRCK / T_{CKSR SR/BY inputs (synchronous)}
T_CINCK / T_{CKCIN CIN Data Inputs (DI) – Getting out from carry chain(3)}
0.28
0.37
0.36
–0.09
0.58
–0.16
0.42
–0.14
1.04
–0.74
0.52
–0.23
0.28
0.31 0.36 ns, Max
0.36
0.41 0.48 ns, Max
0.36
–0.09
0.57
–0.16
0.41
–0.14
1.02
–0.73
0.51
–0.23
0.40
–0.09
0.64
–0.16
0.46
–0.14
1.15
–0.73
0.57
–0.23
0.47
–0.09
0.75
–0.16
0.54
–0.14
1.35
–0.73
0.67
–0.23
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Set/Reset
T_RPW
Minimum Pulse Width, SR/BY inputs
0.54
0.53
0.59 0.70 ns, Min
T_RQ
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
1.05
1.03
1.15 1.35 ns, Max
F_TOG
Toggle Frequency (MHz) (for export control)
1181
1205
1205⁽⁴⁾ 1028 MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent 4VLX/SX
-12 column.
3. These items are of interest for Carry Chain applications.
4. XC4VFX -11 devices are 1181 MHz.
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
31